Hello:
Just starting with FPGA design When the FPGA (cyclone II) drives pins into a device with a specific loading value (i.e 10pf) , is there a calculation or rule thumb to estimate what the drive strength should be set in Quartus for those pins? I know Quartus defaults to maximum and sometimes not all signals are available to connect a scope. Other than simulation, is there way to estimate this? thank you链接已复制
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There can't be a rule of thumb because the best setting also depends on signal speed and required rise time respectively acceptable signal delays. I usually choose minimum current for general purpose I/O, higher values possibly for clock lines or fast memory interfaces.
--- Quote Start --- sometimes not all signals are available to connect a scope --- Quote End --- I think, it's sufficient to connect one signal to an oscilloscope to see the basic effects of current strength settings.--- Quote Start --- There can't be a rule of thumb because the best setting also depends on signal speed and required rise time respectively acceptable signal delays. I usually choose minimum current for general purpose I/O, higher values possibly for clock lines or fast memory interfaces. --- Quote End --- I thought based on the parameters that you indicated (rise time , load capacitance, etc) that an estimated calculation can be made as a start up value. There are few cases as well where there is no chance to get a test point to put a scope on a particular signal. It will be nice in this case to use a theorical estimation instead of using the default setting even if the system is running ok. thanks
--- Quote Start --- You can extract the exact output characteristic for each current strength setting from the IBIS files and calculate the respective dynamical response or use a tool, that does the calculation. --- Quote End --- Would you mind elaborating in what tools and a little more details on how you do this exactly? thanks again
