Driving AdressData on the same Bus

Altera_Forum · ‎11-09-2011

Hi,

Please can somebody give me any advice how the VHDL Code for driving the

A0-A7=D0-D7 with the Latch Register could looks like.

I have been trying without success to solve it.

I would appreciate any response

Regards,

Altera_Forum · ‎11-09-2011

You are talking about the FPGA part to drive the multiplexed bus? Start with sketching a timing diagram.

Altera_Forum · ‎11-09-2011

Ok, but what do you means by sketching the timing Diagram?

I have never done such a thing before.

My entire project looks like the attached file. So the Databus should be used simultaneously by SRAM-I/O and LED.

Please I would appreciate your advice.

Regards,