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Driving multiple PLLs from single clock-capable pin

Altera_Forum
Honored Contributor II
‎05-10-2016 07:07 AM
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Hi, 

I have designed a board with Cyclone-IV E FPGA (EP4CE40CF23C6N). According to this datasheet, this FPGA has 4 PLLs and 4 clock capable pins. I want to know whether it is recommended/safe to drive more than 2 PLLs from a single clock pin. I am asking this because I had driven 4 PLLs from a single pin. The design worked for some time, and after some 4-5 months I observed that the FPGA went bad (VCCINT shorted to GND). I don't whether it is because of PLL issue. In the datasheet screenshot (attached below), it is mentioned that a single pin can drive a single PLL, and another PLL (without compensation). Can someone please clear these doubts. 

regards, 

rajesh
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Altera_Forum
Honored Contributor II
‎05-10-2016 07:13 AM
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Please find Cyclone-IV E clock network attached

Preview file
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Altera_Forum
Honored Contributor II
‎05-10-2016 11:11 AM
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It's certainly 'safe' to do so. However, there are limitations as to which clock pins can drive which PLLs. 

 

Run a design through Quartus. Quartus will only compile your design if it's able to find resources in the device to satisfy your design's requirements. If you can't drive two (or more) PLLs from a particular clock pin Quartus will soon tell you. 

 

Cheers, 

Alex
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