EMIF TOOLKIT failure, see screenshot. Added Hard Memory controller to design, but calibration results show a failure in the EMIF toolkit. what is the source of the error?

[ALee11]

we integrate a HMC (Hard Memory Controllers) in our design. Each such HMC is connected to 40bit DDR3 bus where 32bits used as data and additional 8 bits used for ECC. We try to check the calibration results of this I/F and when running the EMIF toolkit tool experience the following failure in connecting to the device :

 (see attachment)

As you can see, linking the project to the device fails... In our project we have only the DDR3 UniPHY IP connected to JTAG to Avalon MM master bridge. Exactly as described in the following document : https://www.intel.co.jp/content/dam/altera-www/global/ja_JP/pdfs/literature/hb/external-memory/emi_uniphy_ref_emif_toolkit.pdf

Can you suggest a source for this error? Anything we can modify in the JDI file or in compilation? Check anything in regards to JTAG?

[sstrell]

What is your target device? Did you enable EMIF Toolkit accessibility when you parameterized the IP?

Also, you can find much more up-to-date documentation here:

https://www.intel.com/content/www/us/en/programmable/support/support-resources/support-centers/external-memory-interfaces-support.html

#iwork4intel

[ALee11]

I'm using USB blaster II indeed. I'm working w/ Cyclone V E family w/ HMC, so no ARM cortex

Is the cyclone V E device supported? according to this, the cyclone V SOC is not supported, so I am wondering if the E is supported.

section 17.5 of this doc https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/external-memory/emi_ip.pdf

[NurAida_A_Intel]

Dear ALee11,

May I know what Quartus version are you using? And if it is old version then I suggest you to try use newer Quartus version and see if it the error still there or not.

Next, I recommend you to create the example design, place it into same location and re-try the toolkit.

Also, without using emif toolkit, can you try to check the calibration status signal and see it is pass calibration? I am asking this because when there is no pll_ref_clk supply to the emif IP, it will cause the linking fail since the toolkit cannot detect anything from emif ip.

Hope this is helpful 😊

Regards,

NAli1

[ALee11]

is cyclone V "E" supported in the tool at all? Is the restriction just on Cyclone V SOC or Cyclone V SOC AND Cyclone V E as stated in the link in my original post?

[NurAida_A_Intel]

Hi ALee11,

Sorry I overlook your question. Yes, Cyclone V E is supported in the tool. The restriction only for Cyclone V SoC part.

Thanks

Regards,

NAli1