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Mhund2
Beginner
454 Views

Hey all, i'm designing a board using cyclone 10 GX, i'm using the Altera evaluation kit as reference. only one available.

they are using two FPGA clocks:

50mhz for fpga core

100Mhz for fpga user clock

why do they need to seprated clocks ? cant they use one and use PLL to distribute it ?

i want to use FPGA for input from two cameras, and output to high speed serdes. do i really need two oscillators for it or just one should be enough ?

 

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9 Replies
AnandRaj_S_Intel
Employee
198 Views

Hi,

 

why do they need to seprated clocks ? cant they use one and use PLL to distribute it ?

>>Most of the application runs with 50 MHz which is default.& fpga user clock used for transceiver calibration, If you are not using it you can ground the pin(user clock).

>>If the user clock is not present at device power-up, transceiver calibration will be delayed until the clock is available.

>>We can use same oscillator but here key is FPGA resource.

 

i want to use FPGA for input from two cameras, and output to high speed serdes. do i really need two oscillators for it or just one should be enough ?

>>Yes, we can use one oscillators however it depend on the design requirements and FPGA resource used.

 

Let me know if this has helped resolve the issue you are facing or if you need any further assistance.

 

Regards

Anand

Mhund2
Beginner
198 Views

hey thank you ...

actually i need to use the transceiver.

so that means i have to use the user clock ?

 

if i will use one clock, what is the risk ? lack of driving source ?

or should i use two clocks of redundancy ?

AnandRaj_S_Intel
Employee
198 Views

​Hi,

 

so that means i have to use the user clock ?

Yes, It is a mandatory requirement when using transceivers.

 

if i will use one clock, what is the risk ? lack of driving source ?

You can't use user clock has PLL input to distribute. (Fitter can't place the design, we will get pin assignment error)

You have to use two oscillators for your design.

 

Regards

Anand

Mhund2
Beginner
198 Views

let me see if i understand...

i need one clock which will be dedicated for the transceiver, to the fPLL, as mentioned "fPLLs are optimized for use as transceiver transmit PLLs and for synthesizing reference

clock frequencies". and this clock need to be connected to the REFCLK_GXB ?

i need to use LVDS also, so according to altera "I/O PLLs are optimized for use with memory interfaces and LVDS SERDES."

is that mean i need another clock for the LVDS (two camera sensors) ? which need to be connected to CLK_[bank] [p,n] ?

and besides that another clock for the FPGA logic ? which need to be connected also for one of the CLK_[bank] [p,n] ?

 

AnandRaj_S_Intel
Employee
198 Views

​Hi,

 

Yes, Clock need to be connected to REFCLK_GXB.

You can use PLL input CLK_[bank] [p,n] to distribute  clocks for LVDS and FPGA logic.

 

Regards

Anand

Mhund2
Beginner
198 Views

thanks ;-)

any rule of thumb regarding clock value ?

AnandRaj_S_Intel
Employee
198 Views

Check the PLL user guide and device datasheet for frequency range

Mhund2
Beginner
198 Views

OK .

THANKS. I HAVE DONE THAT. BUT STILL one last question.

according to user guide: CLKUSER pin is for transceiver calibration (100-125Mhz) also according to guidelines:

"If you are using the CLKUSR pin for configuration and transceiver calibration, you must supply an external free running and stable clock to the CLKUSR pin at start of device

configuration and also when the device entered user mode. If the clock is not present at device power-up, transceiver calibration will be delayed until the clock is available. "

 

so why have you said to connect the transceiver clock to REFCLK_GXB

or you actually mean the data's clock that entering the transceiver ? and if data is entering on differntial pair (no dedicated clock) ?

 

AnandRaj_S_Intel
Employee
198 Views

Hi,

 

We have to use dedicated (oscillators) free running clock for CLKUSR.

REFCLK_GXB is data's clock that entering the transceiver from another oscillators.

We can use two oscillators with Any-Frequency clock generator to provide clock for REFCLK_GXB & CLK_[bank] [p,n].

 Or

use separate dedicated oscillators.

 

Regards

Anand

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