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EP4CE30F23C8 DDR2 layout

Altera_Forum
Honored Contributor II
‎09-13-2010 09:27 AM
1,111 Views

What are reasonable constrains for DDR2 layout - trace matching 

Data group i did with 15ps +-50mil to DQS 

ADDR/CTRL group within +-100mil to CLK_P/N 

 

What is relationships between DQS and CLK? 

What is acceptable skew between DDR_CLK_P and _N 

 

memories are 0.8" apart from fpga. 

 

DDR2 speed - 533
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Altera_Forum
Honored Contributor II
‎09-15-2010 05:37 AM
408 Views

What anybody isn't lay-out boards here?

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