Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
Announcements
FPGA community forums and blogs on community.intel.com are migrating to the new Altera Community and are read-only. For urgent support needs during this transition, please visit the FPGA Design Resources page or contact an Altera Authorized Distributor.
21615 Discussions

EP4CE30F23C8 DDR2 layout

Altera_Forum
Honored Contributor II
‎09-13-2010 09:27 AM
1,141 Views

What are reasonable constrains for DDR2 layout - trace matching 

Data group i did with 15ps +-50mil to DQS 

ADDR/CTRL group within +-100mil to CLK_P/N 

 

What is relationships between DQS and CLK? 

What is acceptable skew between DDR_CLK_P and _N 

 

memories are 0.8" apart from fpga. 

 

DDR2 speed - 533
0 Kudos

Link Copied

1 Reply
Altera_Forum
Honored Contributor II
‎09-15-2010 05:37 AM
438 Views

What anybody isn't lay-out boards here?

0 Kudos
Copy link
Reply

Community support is provided Monday to Friday. Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.