EPF10K10 area optimization

[Altera_Forum]

Hi! 

 I've noticed a couple of interesting things working with the (yes, old!) EPF10K10 and was hoping that, since it's a mature / vintage device, people could share some area optimization techniques.  So far, I've noticed a couple of things:  - Hard coded state machines are much more effective. I.e. it's cheaper to do: { address, 2'd0 through 2'd3 } than doing { address, index[1:0] } - Order of certain operations makes a difference. Re-ordering a 16-bit ALU (XOR, ADD and ADD and pass-through) in a multiplexer can save up to 16 LE's. when you start with the XOR.  I'm sure there are more?  Thanks!  -Mux

[Altera_Forum]

In the ancient days of MAX+Plus II the coding style definitely made a difference. However, this is mainly related to the algorithms used in the tool, rather than limitations of the device. 

 The same will hold for Quartus 9.0SP2. If you take the same coding style and apply it to a device that both 9.0SP2 and 12.1 supports, eg., a Cyclone or Stratix series device, you'll likely see that the logic generated by 12.1 is probably identical for several different coding styles that used to produce different logic.  The price of progress :)  Cheers, Dave