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AGofs
Novice
349 Views

Emulated LVDS outputs and Quartus pin planner

At "CycloneV device handbook" wrote: "Emulated LVDS, RSDS and mini-LVDS output buffers use two single-ended output buffers with an

external single-resistor or three-resistor network, and can be tri-stated.". So, I've used ALTIOBUFF mega-function in order to implement emulated LVDS signal. There are 2 buffers: one to Positive signal and one to negative(inverted positive) signal. Everything compiles at Modelsimand simulation works properly. But when I'm trying to assign FPGA emulated LVDS pins to output signals in my top level design,then Quartus-II (18.1, Lite) Pin Planner splits top level Positive signal to positive and negative signal, and top level Negative signal to positive and negative. In others words Pin Planner duplicates all output pins. How can I assign positive and negative output signal (from my top level design ) to FPGA pins?

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6 Replies
36 Views

I think if you are using single ended buffer ,then the IO Standard should change to single end.Can you check your IO standard setting in the assignment editor ?

 

Thank you ,

 

Regards,

Sree

AGofs
Novice
36 Views

Good morning Sree,

Thank you for your replay.

AGofs
Novice
36 Views

The question is: if should I to implement these two single-ended output buffers with ALTIOBUFF mega-function or Quartus-II will add them automatically?

 

36 Views

As per my understanding you have to use the ALTIOBUFF IP to instantiate the Buffer. You can check with design without adding and with in RTL viewer. :)

 

Thank you,

 

Regards,

Sree

AGofs
Novice
36 Views

Good afternoon Sree,

I'll try to describe the problem once again:

I've used to write the code at ModelSim before loading it Quartus.

It is very important at ModelSim to describe all output ports: positive and negative.

Then I'm importing all the project into Quartus II.

When I'm trying with Pin Planner to connect an output ports (negative and positive) to matching pins (emulated LVDS format),

then Quartus II splits outputs (Negative and Positive ports of the project) into Negative and positive node each.

For example: I have to get out from FPGA with 4 emulated LVDS pairs of signals : CLK_N(0 to 3) and CLK_P(0 to 3).

So, there are 8 output ports CLK_N(0 to 3) and CLK_P(0 to 3) at ModelSim Top level entity.

When I'm trying to connect ModelSim Top Level Ports with emulated LVDS dedicated pins (of FPGA) with Pin Planner ,then

Quartus-II splits CLK_N(0) to CLK_N(0) and CLK_N(n)(0) ,

CLK_P(0) to CLK_P(0) and CLK_P(n)(0), etc.

Therefore, the question is:

1)How can user connect an existing output ports to the emulated LVDS dedicated pins by Pin Planner without splitting?

If I'm writing at ModelSim Top level entity only CLK_P(0 to 3) (without CLK_N(0 to 3) 'then I can connect these ports to emulated LVDS dedicated pins without splitting.

The Quartus-II will complete negative "Node Name" automatically.

But ModelSim entity includes only half of the needed ports (positive ones).

Therefore the question is:

How can I connect Quartus generated Node names with ModelSim Top entity ports?

 

36 Views

i am sorry for late response ,Actually caught into other stuff and didn't pay attention my open issues.I think you can do simulation after the buffer level (ie Single ended) and when you use in quartus XX_n pin automatically assigned by quartus if the IO std selected correctly.

 

Is that make sense ?

 

Thank you ,

 

Regards,

Sree