Enabling series termination on 1.0V and 3.3V IOs in MAX10 FPGA

[noujaz]

Hi All,

Can I enable series termination on 1.0V IOs of MAX10 FPGA. "MAX 10 General Purpose I/O User Guide" does not mention series termination options for 1.0V and 3.3V IOs. Also when I tried adding series termination on 1.0V and 3.3V IOs in Quartus pin planner, the fitter is failing. Can you please help me on this.

Thanks in advance,

Noujaz

[ak6dn]

In the MAX10 GPIO User Guide, per Table 13. Selectable I/O Standards for RS OCT indicates that On Chip Termination (OCT) is only available for 1.2V thru 3.0V LVCMOS, 1.8V thru 3.0V LVTTL, as well as SSTL and HSTL outputs. Not possible for 1.0V or 3.3V LVCMOS. So you are trying to select an option that is not possible, and Quartus is letting you know that.

[AminT_Intel]

Hello,

Yes, the designer need to refer to our documents for FPGA limitations. I will close this case in 3 days if there is no further question from you.

Thank you.

[noujaz]

Hi,

Thanks for your input. I have one more question here. What will happen if I declare the IO pins in a bank as 1.2V in the Quartus Pin Planner and connect 1.0V to FPGA VCCIO pins on the board? I will make sure the source and destination IOs are working on 1.0V voltage so that the pins will not get damaged. If this is possible I can enable series termination inside FPGA on the lines I need.  

Thanks,

Noujaz

[ak6dn]

Well, in that case you would be using those I/Os out of spec.

Most likely they still might work, but you will likely find slower slew rates/timing and/or reduced noise margin.

So if this is a one off design for use at room temperature you will likely find it still works.

But if this is a volume commercial design expected to work over the full device temperature/voltage range, then who knows.

If you do get failures, you can't go back to Intel and complain that their 1.2V I/Os are not working as expected at 1.0V.

You will be on your own at that point.

Your profile says you are an Intel employee, correct?