Error (10119): Verilog HDL Loop...must terminate within 250 iterations

[Altera_Forum]

Hello @all, 

 I have a problem with a Verilog module where I use a for-loop to drive the processesing of a blob detection.  The module receives a register which contains the X- and Y-Coordinate of the start position and the length of a detected line, which belongs to a blob. If a pixel belongs to a blob depends only on the intense of the color values (RGB).  But the problem is that I get the following error message, if I try to synthesize the code:  Error (10119): Verilog HDL Loop Statement error at blob_center_computation.v(68): loop with non-constant loop condition must terminate within 250 iterationsMaybe I am on the wrong way. Is it even possible to use for-loops for the FGPA architecture?  Btw. I am using a Altera DE2 Development and Education Board with a Cyclone II  Thanks for any comments.  kind regards, Alex

[Altera_Forum]

In a HDL (hardware definition language), iteration schemes have a different meaning than in procedural programming languages. They don't define sequential processing of the included statements but are a method to define parallel processing. Even if the iteration construct would be accepted by the Veriolog compiler (when using constant loop parameters), the resource requirement would go beyond any meaningful FPGA size. 

 Interestingly, the 50 MHz clock isn't used at all in your code, but it should be. The only suitable way is to perform the calculation sequentially, one step for each clock cycle.

[Altera_Forum]

Thank you, that helps me a lot. 

I was quite sure that I have some vacancies in my basic knowledge.