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Hi,
I called in a CPRI IP from Altera Quartus II which created a testbench tb_altera_cpri. While trying to compile this testbench I encountered an error: Error (10533): VHDL Wait Statement error at tb_altera_cpri.vhd(839): Wait Statement must contain condition clause with UNTIL keyword. Can anyone help me please? CheersLink Copied
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--- Quote Start --- Hi, I called in a CPRI IP from Altera Quartus II which created a testbench tb_altera_cpri. While trying to compile this testbench I encountered an error: Error (10533): VHDL Wait Statement error at tb_altera_cpri.vhd(839): Wait Statement must contain condition clause with UNTIL keyword. Can anyone help me please? Cheers --- Quote End --- Post the line of code - line 839. You are trying to compile this in Modelsim right? Quartus should not be used for the testbench. Cheers, Dave
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Hi Dave,
Yes. Its line 839. Is it anyway possible to look at the RTL viewer using this testbench? I tried compiling with ModelSim, I faced another error saying, "Error: Error loading design # Pausing macro execution # MACRO ./compile_vhdl.do PAUSED at line 65"- Mark as New
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--- Quote Start --- Yes. Its line 839. --- Quote End --- We both know that. I wanted you to post the code so I could confirm it was valid VHDL. --- Quote Start --- Is it anyway possible to look at the RTL viewer using this testbench? --- Quote End --- The RTL viewer is a Quartus tool, so no, you cannot view the testbench using RTL viewer. Viewing a testbench makes no sense, given that most of the logic does not create RTL. Testbenches contain non-synthesizeable constructs. --- Quote Start --- I tried compiling with ModelSim, I faced another error saying, "Error: Error loading design # Pausing macro execution # MACRO ./compile_vhdl.do PAUSED at line 65" --- Quote End --- I haven't seen that one before. How are you trying to simulate in Modelsim - using Nativelink or from within Modelsim directly? Cheers, Dave
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--- Quote Start --- We both know that. I wanted you to post the code so I could confirm it was valid VHDL. The RTL viewer is a Quartus tool, so no, you cannot view the testbench using RTL viewer. Viewing a testbench makes no sense, given that most of the logic does not create RTL. Testbenches contain non-synthesizeable constructs. I haven't seen that one before. How are you trying to simulate in Modelsim - using Nativelink or from within Modelsim directly? Cheers, Dave --- Quote End --- "I haven't seen that one before. How are you trying to simulate in Modelsim - using Nativelink or from within Modelsim directly?" - I am running it straight from within Modelsim. Cheers
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--- Quote Start --- I am running it straight from within Modelsim. --- Quote End --- So what generated ./compile_vhdl.do, and what is at line 65? The error messages indicate where you need to look. Asking these types of questions on the forum without some sort of detail is pretty pointless. Cheers, Dave
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--- Quote Start --- The error messages indicate where you need to look. Asking these types of questions on the forum without some sort of detail is pretty pointless. --- Quote End --- Nevertheless there's is one answer I can give you without seeing the code: Pay attention to VHDL syntax rules and the error will disappear.
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hi all;
i have the same problems as sharmakn. while trying to compile project, Quartus II 11.1 Web Edition says: Error (10533): VHDL Wait Statement error at DS_timer.vhd(23): Wait Statement must contain condition clause with UNTIL keyword And this's my code : entity DS_timer is port( clk : in std_logic; start : in std_logic; stop : in std_logic; reset : in std_logic; min : out std_logic_vector(6 downto 0); sec1 : out std_logic_vector(6 downto 0); sec2 : out std_logic_vector(6 downto 0)); end DS_timer; Architecture behavioral of DS_timer is begin process variable temp1 : integer range 0 to 10; variable temp2 : integer range 0 to 6; variable temp3 : integer range 0 to 10; begin wait on reset,clk,start,stop; -- ERROR if (reset='1') then temp1:=0;temp2:=0;temp3:=0; elsif (clk'event and clk='1') then if (start='1') then wait until stop='0'; temp1:=temp1+1; if (temp1=10) then temp1:=0; temp2:=temp2+1; if (temp2=6) then temp2:=0; temp3:=temp3+1; if (temp3=10) then temp3:=0; end if; end if; end if; end if; end if; --7 code segment-- ....................................................................... end behavioral; Am I wrong?Can anyone help? Thanks- Mark as New
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Quartus tells you, that this wait syntax isn't supported for synthesis.
The sensitivity list should be specified with the process statement. In case of doubt refer to the VHDL templates accessible in the Quartus editor. According to the code, only reset and clock are meaningful members of the sensitivity list.- Mark as New
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--- Quote Start --- Quartus tells you, that this wait syntax isn't supported for synthesis. The sensitivity list should be specified with the process statement. In case of doubt refer to the VHDL templates accessible in the Quartus editor. According to the code, only reset and clock are meaningful members of the sensitivity list. --- Quote End --- thank , problem solved !
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I just encountered the same problem. This happened when I accidentilly set the testbench file as top level entity. So as long as you don't do that, and keep to the correct syntax, you should be fine.
--this line is here just to make the post long enough.
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