Error: avalon_st_adapter_001.data_format_adapter_0: The output interface has no empty signal, but this adapter has been configured to adapt a narrow input interface symbols per beat(6) to a wide output interface symbols per beat(12).
There is no mismatch between source and sink interfaces as far as databitspersymbol and symbols per beat. I created a custom adapter that solves uncommon signal issues between interfaces (the empty and ready signals), but I still keep getting this error. Interesting part is that I could generate HDL in QSYS if I remove irrelevant modules. Did anyone experience such issue?
