Error with F-Tile Example Design Hardware Test: Reset Probe Value

[allenS1]

Hello,

I brought up an example design for F-Tile Ethernet Hard IP, and I'm trying to run the hardware test for it. I'm using Intel Agilex I-Series Transceiver-SoC Development Kit with a single instance of the IP core. Design example compiled with no errors and programmed successfully. When I try to open System Console and run the hardware test with internal loopback (run_test), it gets through some of the test with printing the PHY Status, but stops short because the value from the reset probe is not what the test was expecting. Here is the output of the test:

Applying Rx Reset

Reading Loop Back Register Status

reg1_xcvr0 0x00000000

reg2_xcvr0 0x42010005

Loop Back for Lane 3 ..

Writing 1st loopback data for Lane 3

Reading Loop Back Registers

reg1_xcvr0 lane 3 0x00000000

reg2_xcvr0 lane 3 0x42010005

Writing 2nd loopback data for Lane 3

Reading Loop Back Registers

reg1_xcvr0 lane 3 0x00000000

reg2_xcvr0 lane 3 0x42010005

Releasing Rx Reset

Checking Status of the Flux Register

lane 0 0x00000000

lane 1 0x00000000

lane 2 0x00000000

lane 3 0x00000000

--- Wait for RX clock to settle... ---
--------------------------------------

-------- Printing PHY status ---------
--------------------------------------

RX PHY Register Access: Checking Clock Frequencies (KHz)

TXCLK :327680 (KHZ)
RXCLK :0 (KHZ)

TX PLL Lock Status 0x00000000

Rx Frequency Lock Status 0x0000aa47

RX PCS Ready 0x0

TX Lanes Stable 0x1

Deskewed Status 0x0

Link Fault Status 0x00000563

Rx Frame Error 0x42010005

Rx AM LOCK Condition 0x00000000

Value from issp reset probe is 0xed/0b11101101
ERROR:rx_pcs_ready is not asserted or link fault is detected. Expected value from issp reset probe is : 0xff

---------------- Done ----------------

When I set the jtag  number, The reset probe was set to 0xed instead of 0xff. Here is the output of the set_jtag 0 command:

Currently selected master is 0:
/devices/10M16S(A|C|L)@2#1-4.1.4.2.3#Agilex I-Series SOC Dev Kit#10.219.70.15:33867/(link)/JTAG/(110:132 v1 #0)/phy_0/master
Applying reset through ISSP
current value : 0b0
Info: Reset applied
Value from issp reset probe is 0xed/0b11101101

I tried going into In System Sources and Probes to manually toggle the resets, but the reset probe value still stays at 0xed. In the error from the hardware test, it says that rx_pcs_ready is not asserted, so it's possible the issue could be with the receiver, but I'm not completely sure. I should also mention that I'm accessing the board remotely so I don't have physical access to it myself. Is there a fix to this so that the hardware test will run successfully?

Allen 

[Paveetirra_Srie]

Hi,

Apologize for the delay.

Please give me a little time to investigate this issue, I will contact you back as soon as I find a possible solution.

Regards,

Pavee

[allenS1]

Hi Pavee,

Thanks for taking the time to look into this. Looking forward to your response.

Best,

Allen

[Paveetirra_Srie]

Hi,

Apologize for the delay. Have you checked the signals and clocks in signaltap?

Regards,

Pavee

[Paveetirra_Srie]

We do not receive any response from you to the previous question that I have provided. This thread will be transitioned to community support. 

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