Execute gate level simulation, the read empty signal of the FIFO is unknown

[Altera_Forum]

http://www.alteraforum.com/forum/attachment.php?attachmentid=11743&stc=1  

simulation:gate level simulation Where,the ADbuffer rdempty signal is the rdempty pin of the FIFO ,I don't know why the signal turs to an unknown state after some time.

[Altera_Forum]

Are you accidently driving ADbuffer_rdempty from the testbench?

[Altera_Forum]

always@(negedge clk or negedge rst_n)  

begin  if (~rst_n)   begin  ADbuffer_rdempty_r1 <= 1'b0;  end   else if(~ADbuffer_rdempty)  begin   ADbuffer_rdempty_r1 <= ~ADbuffer_rdempty;  end  else  begin   ADbuffer_rdempty_r1 <= ADbuffer_rdempty_r1;  end end  assign ADbuffer_rdreq = ADbuffer_rdempty_r1 & (!ADbuffer_rdempty);  ADbuffer_rdempty is the rdempty signal of the FIFO. The wrclk of the FIFO is 80MHz,and the rdclk of the FIFO is 125MHz&#65292;when the FIFO is not empty ,I will read the data in the FIFO. The Verilog code above is the rdreq created .