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Altera_Forum
Honored Contributor I
1,260 Views

FPGA LVDS bank VCCIO issue

In a custom board we created, it is required to use LVDS pins in two banks. I know that the VCCIO of the corresponding bank should be 2.5V. Unfortunately the VCCIO was connected to 3.3V instead of 2.5V by mistake. 

Can LVDS still work? 

The bank has LVDS input data pin and input CLK and output data.
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5 Replies
Altera_Forum
Honored Contributor I
82 Views

It will 'work' but won't conform to the timings specified in the datasheet. If you only have LVDS input signals then, perhaps, it will simply work as you hope. Output LVDS signals would be a different issue. 

 

Either way - whether it appears to work or not - I recommend you correct the design error. 

 

Cheers, 

Alex
Altera_Forum
Honored Contributor I
82 Views

This FPGA (Cyclone 5 btw) will talk to another FPGA (Cyclone 4) through LVDS. 

Will output LVDS signals be an issue? 

 

Fixing the design will require few weeks for new board manufacturing. I was hoping to test the whole system first because there are other components, .....
Altera_Forum
Honored Contributor I
82 Views

Is there no way of modifying the board such that you feed that bank with the right voltage? 

 

LVDS output signals will simply be a little misshaped. Being a current based signalling standard, the IO circuitry - driven at 3.3V - will be able to drive the rising/falling edges faster. They're unlikely to damage the Cyclone IV and it will most likely just work. However, you will be operating your devices out of spec. So, Altera won't support you should you suddenly start burning out parts - something I think unlikely to happen but it's still a potential issue. 

 

Cheers, 

Alex
Altera_Forum
Honored Contributor I
82 Views

The main problem is that the 3.3V is supplied to few other components and banks and I cannot just modify it. If I fed it with 2.5V, other FPGA banks may not be able to communicate with other chips. 

 

I will try to reduce the voltage to 3V and try to power and test the system. I hope it works even for just testing. New boards should be designed later. 

 

Thanks.
Altera_Forum
Honored Contributor I
82 Views

The input differential clock is seen successfully inside the FPGA. I have other problems with the chip and opened another thread for them.

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