FPGA Monitor Program 18.1 Tutorial: Could not query JTAG Instance IDs. Please ensure the FPGA has be

[phiho]

Greetings,

I have been following the instructions in "Intel FPGA Monitor Program
Tutorial for ARM.pdf" with "Intel FPGA Monitor Program"  version 18.1 to work with the board DE10-Nano.

The result was not successful. Please find appended below the transcript of the "Info&Errors".

Please also find attaches a series of screen capture of the process following the instructions from the above said tutorial documentation.

Please advise if I missed something.  Please advise if you need more screen captures.

Regards,

phiho

Writing the makefile: F:/de10-nano/Tutorials/FPGA_Monitor/18.1/arm/makefile
cd F:/de10-nano/Tutorials/FPGA_Monitor/18.1/arm/; make clean
make: *** No rule to make target `clean'. Stop.
Writing the makefile: F:/de10-nano/Tutorials/FPGA_Monitor/18.1/arm/makefile
cd F:/de10-nano/Tutorials/FPGA_Monitor/18.1/arm/; make clean
make: *** No rule to make target `clean'. Stop.
G:/intel/FPGA/Lite/18.1/quartus/bin64/quartus_pgm -c "DE-SoC [USB-1]" --auto
1) DE-SoC [USB-1]
4BA00477 SOCVHPS
02D020DD 5CSEBA6(.|ES)/5CSEMA6/..
Info: *******************************************************************
Info: Running Quartus Prime Programmer
Info: Version 18.1.1 Build 646 04/11/2019 SJ Lite Edition
Info: Copyright (C) 2019 Intel Corporation. All rights reserved.
Info: Your use of Intel Corporation's design tools, logic functions
Info: and other software and tools, and any partner logic
Info: functions, and any output files from any of the foregoing
Info: (including device programming or simulation files), and any
Info: associated documentation or information are expressly subject
Info: to the terms and conditions of the Intel Program License
Info: Subscription Agreement, the Intel Quartus Prime License Agreement,
Info: the Intel FPGA IP License Agreement, or other applicable license
Info: agreement, including, without limitation, that your use is for
Info: the sole purpose of programming logic devices manufactured by
Info: Intel and sold by Intel or its authorized distributors. Please
Info: refer to the applicable agreement for further details, at
Info: https://fpgasoftware.intel.com/eula.
Info: Processing started: Sat Jan 23 04:28:56 2021
Info: Command: quartus_pgm -c "DE-SoC [USB-1]" -m jtag -o P;G:/intel/FPGA/Lite/18.1/University_Program/Computer_Systems/DE10-Nano/DE10-Nano_Computer/verilog/DE10_Nano_Computer.sof@2
Info (213045): Using programming cable "DE-SoC [USB-1]"
Info (213011): Using programming file G:/intel/FPGA/Lite/18.1/University_Program/Computer_Systems/DE10-Nano/DE10-Nano_Computer/verilog/DE10_Nano_Computer.sof with checksum 0x0B07E6FB for device 5CSEBA6U23@2
Info (209060): Started Programmer operation at Sat Jan 23 04:29:01 2021
Info (209016): Configuring device index 2
Info (209017): Device 2 contains JTAG ID code 0x02D020DD
Info (209007): Configuration succeeded -- 1 device(s) configured
Info (209011): Successfully performed operation(s)
Info (209061): Ended Programmer operation at Sat Jan 23 04:29:04 2021
Info: Quartus Prime Programmer was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 4465 megabytes
Info: Processing ended: Sat Jan 23 04:29:04 2021
Info: Elapsed time: 00:00:08
Info: Total CPU time (on all processors): 00:00:04
cd F:/de10-nano/Tutorials/FPGA_Monitor/18.1/arm/; make clean
make: *** No rule to make target `clean'. Stop.
cd F:/de10-nano/Tutorials/FPGA_Monitor/18.1/arm/; make compile
make: *** No rule to make target `compile'. Stop.
cd F:/de10-nano/Tutorials/FPGA_Monitor/18.1/arm/; make compile
make: *** No rule to make target `compile'. Stop.
Could not query JTAG Instance IDs.
Please ensure the FPGA has been configured using the correct .sof file.

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FPGA-Tutorial-Fig13-ActionCompile.jpg

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[#2]

Greetings,

I have been following the instructions in "Intel FPGA Monitor Program
Tutorial for ARM.pdf" with "Intel FPGA Monitor Program"  version 18.1 to work with the board DE10-Nano.

The result was not successful. Please find appended below the transcript of the "Info&Errors".

Please also find attaches a series of screen capture of the process following the instructions from the above said tutorial documentation.

Please advise if I missed something.  Please advise if you need more screen captures.

Regards,

phiho

Writing the makefile: F:/de10-nano/Tutorials/FPGA_Monitor/18.1/arm/makefile
cd F:/de10-nano/Tutorials/FPGA_Monitor/18.1/arm/; make clean
make: *** No rule to make target `clean'. Stop.
Writing the makefile: F:/de10-nano/Tutorials/FPGA_Monitor/18.1/arm/makefile
cd F:/de10-nano/Tutorials/FPGA_Monitor/18.1/arm/; make clean
make: *** No rule to make target `clean'. Stop.
G:/intel/FPGA/Lite/18.1/quartus/bin64/quartus_pgm -c "DE-SoC [USB-1]" --auto
1) DE-SoC [USB-1]
4BA00477 SOCVHPS
02D020DD 5CSEBA6(.|ES)/5CSEMA6/..
Info: *******************************************************************
Info: Running Quartus Prime Programmer
Info: Version 18.1.1 Build 646 04/11/2019 SJ Lite Edition
Info: Copyright (C) 2019 Intel Corporation. All rights reserved.
Info: Your use of Intel Corporation's design tools, logic functions
Info: and other software and tools, and any partner logic
Info: functions, and any output files from any of the foregoing
Info: (including device programming or simulation files), and any
Info: associated documentation or information are expressly subject
Info: to the terms and conditions of the Intel Program License
Info: Subscription Agreement, the Intel Quartus Prime License Agreement,
Info: the Intel FPGA IP License Agreement, or other applicable license
Info: agreement, including, without limitation, that your use is for
Info: the sole purpose of programming logic devices manufactured by
Info: Intel and sold by Intel or its authorized distributors. Please
Info: refer to the applicable agreement for further details, at
Info: https://fpgasoftware.intel.com/eula.
Info: Processing started: Sat Jan 23 04:28:56 2021
Info: Command: quartus_pgm -c "DE-SoC [USB-1]" -m jtag -o P;G:/intel/FPGA/Lite/18.1/University_Program/Computer_Systems/DE10-Nano/DE10-Nano_Computer/verilog/DE10_Nano_Computer.sof@2
Info (213045): Using programming cable "DE-SoC [USB-1]"
Info (213011): Using programming file G:/intel/FPGA/Lite/18.1/University_Program/Computer_Systems/DE10-Nano/DE10-Nano_Computer/verilog/DE10_Nano_Computer.sof with checksum 0x0B07E6FB for device 5CSEBA6U23@2
Info (209060): Started Programmer operation at Sat Jan 23 04:29:01 2021
Info (209016): Configuring device index 2
Info (209017): Device 2 contains JTAG ID code 0x02D020DD
Info (209007): Configuration succeeded -- 1 device(s) configured
Info (209011): Successfully performed operation(s)
Info (209061): Ended Programmer operation at Sat Jan 23 04:29:04 2021
Info: Quartus Prime Programmer was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 4465 megabytes
Info: Processing ended: Sat Jan 23 04:29:04 2021
Info: Elapsed time: 00:00:08
Info: Total CPU time (on all processors): 00:00:04
cd F:/de10-nano/Tutorials/FPGA_Monitor/18.1/arm/; make clean
make: *** No rule to make target `clean'. Stop.
cd F:/de10-nano/Tutorials/FPGA_Monitor/18.1/arm/; make compile
make: *** No rule to make target `compile'. Stop.
cd F:/de10-nano/Tutorials/FPGA_Monitor/18.1/arm/; make compile
make: *** No rule to make target `compile'. Stop.
Could not query JTAG Instance IDs.
Please ensure the FPGA has been configured using the correct .sof file.