I have recently acquired the Cyclone V GT Development Board https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=167&No=843 , my first Intel board moving over from Xilinx boards. I'm having trouble getting my clock signal to work. I'm trying to use a very simple design, toggling an LED based on a counter. I have also added a simple forwarding signal between buttons and LED's, to check that the upload is working correctly (it is).
However, my counter and LED simply do not seem to work. I've tried using multiple clock signals as identified on pages 2-20 and 2-21 in the reference manual (http://www.altera.com/literature/manual/rm_cvgt_fpga_dev_board.pdf), but no matter which one I choose, the output is the same (the led regOut is constantly lit, meaning a logic 0 is driven onto the LED). I have attached the reset to a sliding switch, and have tried uploading the configuration with the switch in either configuration.
I have attached an image of my current pin mappings as well as the verilog code in question.
(As an aside: I'm also getting an error stating that all of my pin assignments are incomplete. I don't understand why this message is popping up. Any explanations?)
Have you tried to simulate the design to check the functionality?
For incomplete assignment, you may check if you have set all the I/O assignments to the affected pins (pin location, I/O standard, etc). Use the Assignment Editor or the Pin Planner to add the missing I/O assignments to the affected pins.
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