FPGA to HPS AXI Bridge Slave Timing Diagram

[Altera_Forum]

Hello, 

 Could someone please provide some timing diagrams for the FPGA to HPS AXI Bridge Slave's timing diagrams?   How are the following signals supposed to be used in order to store memories properly. I am need make a counter that stores a number into each address consecutively.  AWID AWADDR AWLEN AWSIZE AWBURST AWLOCK AWCACHE AWPROT AWVALID AWREADY AWUSER WID WDATA WSTRB WLAST WVALID WREADY  Thanks!  Jack