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FPGA-to-HPS bridge data width on Agilex-7 M-series

Mikhail_a
Novice
713 Views

Hello

I'm working with Agilex 7 AGM039 device and in platform designer I see that data width of FPGA-to-HPS bridge has only 2 valid options: 128b and 256b, while with Agilex 7 I-series it has 512b option(FPGA-to-HPS Bridge). Also in documentation for Agilex 7 HPS I didn't find any mentions that data width doesn't have 512b option. 

 

So my question is whether it is an undocumented feature or there is something wrong with my Quartus?

Quartus version is 23.4 and Platform Designer 23.4 Build 79.

Mikhail_a_0-1708793574119.png

 

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EBERLAZARE_I_Intel
524 Views

Hi,


From our factory team, the Agilex 7 M-series is 128/256 bit.


We will update our documentation on this info.


View solution in original post

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6 Replies
EBERLAZARE_I_Intel
647 Views

Hi,


Allow me sometime to double check with our internal team on that settings for Agilex 7 M-series.


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EBERLAZARE_I_Intel
593 Views

Hi,


We are getting some final confirmation, will get back to you soon.


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Mikhail_a
Novice
582 Views

Hello!

 

That's good, thank you.

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EBERLAZARE_I_Intel
525 Views

Hi,


From our factory team, the Agilex 7 M-series is 128/256 bit.


We will update our documentation on this info.


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Mikhail_a
Novice
512 Views

Hello

Thank you for your answer!

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EBERLAZARE_I_Intel
465 Views

Hi,


I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.



p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.


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