[FPGA-to-SDRAM Avalon-MM Bridge] -> beginbursttransfer is missing...

[Altera_Forum]

Hi All, 

 I'm working with the ArriaV device and going to use the FPGA-to-SDRAM Avalon-MM Bridge.   Does the FPGA-to-SDRAM Avalon-MM Bridge support the burst transactions?   After enabling the FPGA-to-SDRAM Avalon-MM Bridge in HPS, the following ports were added to HPS instance:  hps_0_f2h_sdram0_data_address  hps_0_f2h_sdram0_data_burstcount  hps_0_f2h_sdram0_data_waitrequest  hps_0_f2h_sdram0_data_writedata  hps_0_f2h_sdram0_data_byteenable  hps_0_f2h_sdram0_data_write   The beginbursttransfer port was not added (doesn't present in the FPGA-to-SDRAM Avalon-MM Bridge in HPS)...   So, my question is whether the FPGA-to-SDRAM Avalon-MM Bridge support the burst transactions? If it does support, how could it work without the beginbursttransfer signal? How could the Avalon Slave (SDRAM Controller) know when capture the address and burstcount lines from the Avalon Master (FPGA)?  Thank you!

[Altera_Forum]

What's the maximum memory space in SDRAM/DDR Memory could be occupied through the FPGA-to-SDRAM Avalon-MM Bridge?  

 Here are my calculations: FPGA-to-SDRAM Bridge has 27 address lines and 256 data lines.  So, 2^27*256=2^27*32B=2^32B=4gb -> 4gb of SDRAM/DDR Memory might be occupied through the FPGA-to-SDRAM Bridge. Is that correct?  What's the mapping? Should the 0x0000_0000 on the address lines of the FPGA-to-SDRAM Bridge indicate that the data will be also written to the address 0x0000_0000 in the SDRAM/DDR Memory?   Thank you!

[Altera_Forum]

I would think it would support burst transactions. The latest Avalon Manual suggests that the "beginbursttransfer" signal is deprecated. On page 3-8 of said manual it says in describing the signal "Altera recommends that you do not use this 

signal. This signal exists to support legacy memory controllers." (which, incidentally, includes the v15.1 Multi-Port Front-End controller which does have a beginbursttransfer signal. :-)  I think it assumes you're doing a burst if you've set burstcount appropriately. It will capture the signal on the first cycle that "read" or "write" are set.  Cheers.

[Altera_Forum]

OK, understood, thank you a lot!

[Altera_Forum]

--- Quote Start ---  OK, understood, thank you a lot!  --- Quote End ---    I'm actually curious about this as I've heard some odd things about AXI support in the Avalon network generated by Qsys. I don't see why it wouldn't support burst transfers, but remember that you're going from an Avalon-MM to an AXI/Avalon slave. I have no idea how the SDRAM module handles the protocol translation!