Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
21323 Discussions

FPGA2SDRAM subsystem

Altera_Forum
Honored Contributor II
1,613 Views

Hello all, 

 

I'd like to use FPGA2SDRAM subsystem. Thus i added 2 ports in HPS properties in Qsys (mm read & mm write). 

I generated preloader and u-boot and put them in mmcblockp3 of my sdcard. 

From hardware side, i got no problem, i managed to read and write in the sdram (according to signaltap). 

 

My issue is now how to write/read in that sdram from arm? What code should i write? What is the adrdess range?... 

 

By advance, 

 

Thanks 

 

Nicolas
0 Kudos
3 Replies
Altera_Forum
Honored Contributor II
467 Views

Hi, 

 

the ARM could write the whole RAM connected to the HPS-Side. 

How to write and read, depends on many factors, such as if you are using Linux, if you need to cache the Memory-Region, etc. 

 

Please be so kind to tell a bit more of your needs.
0 Kudos
Altera_Forum
Honored Contributor II
467 Views

Hi,  

 

I reached to read/write from the ARM thanks to mmap function. 

What is "cache the Memory-Region" ? (sorry bit dummy in software)
0 Kudos
Altera_Forum
Honored Contributor II
467 Views

The ARM has Caches. In order to the size of the Caches and depending on your needs it could be more efficient to bypass the cache for some data...

0 Kudos
Reply