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Hi,
I am using a MAX-II Cpld to fulfill the FPP configuration for a Cyclone4gx fpga. The cpld is designed with a flash loader (full function). It was working in my previous design. this time in my current design i only change the bank 1 (w/ JTAG) Vccio from 3.3V to 2.5V with other banks voltages and Vccint unchanged which are all 1.8V. My Cpld chip is EPM2210GF256C3N. When i program it by using Quartus-II PC programmer (Q-II, v13.1) it failed and said " Flash Loader IP is not loaded in cpld ". Is there anyone who can help me? Urgent! Very appreciated! YaotingLink Copied
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On the face of it the changes you state that you have made shouldn't stop the FPP functionality working. Just to confirm - you haven't changed the pinout or rtl from one design to the next?
--- Quote Start --- When i program it by using Quartus-II PC programmer --- Quote End --- By 'it' I assume you're referring to configuration of the FPGA? Can you confirm that you can successfully configure the CPLD? Assuming you have not changed anything else, have you confirmed you can use your previous design with Quartus v13.1? Have you tried a previous release (try 12.1sp1) on your new hardware? Final thought, the FLASH loader IP isn't something you're missing license for, is it? Is Quartus v13.1 pointing at an appropriate license?- Mark as New
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No, i did not change any design and pinout in CPLD.
Good reminder of the license issue! I have recently upgraded the Quartus to v13.1 by new license. I've recompiled the CPLD and now the CPLD looks properly configured and i can see the programer can program the flash memory. Unfortunately it stops at the beginning of CRC verification. I do not know why. Any clue? Thanks very much!- Mark as New
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When i reprogram the old design which was working, it fails similarly, stopping at CRC beginning. Why? Could be a Quartus software issue or license issue? I tried to use the Quartus II v13.0 which worked before i upgrade my Quartus II sw. Same thing, it fails too. Now i am totally stuck there. No idea.
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It could be a Quartus issue, but experience tells me these problems usually appear with a new major release (e.g. 13.0) and are fixed by the time the first major update appears (e.g. 13.1), which you have.
I'm now assuming you're old hardware worked with a previous release of Quartus - pre 13.0. Can you try that? If that does work it would be worth raising a case with Altera. I have seen issues of programming halting at CRC checking. This has always been because the FLASH hasn't actually been programmed with anything - often because something has hold of the control bus during programming. However, this isn't flagged by the programmer until it checks the CRC. This could be the case with your system, which might point at the CPLD. Does anything else have access to the FLASH control signals? Is there an arbitration issue? Regards, Alex- Mark as New
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Hi Alex,
Thank you for your response. As i mentioned in last message, i did go back to the old version of the Q II and tried to reprogram my old board, which had worked with V13.0. Unfortunately, it fails with same phenomena. Yaoting
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