Fail to Boot Software from EPCS16

[Altera_Forum]

Hi, 

I have made a simple custom system with a EP3C16Q240, EPCS16,SDRAM,an AS connector,a JTAG connector and a 50Mhz system clock in which MSEL[0:2]=[010],VCCIO=3.3V.The SOPC contains a cpu with reset vector=EPCS_controller and exception vector=sdram,an 8k on chip ram,an 8k on rom,an EPCS_controller with base address 0x00000000,a jtag_uart,a system ID,a sdram conytoller,a test_uart,a 8bit pio. What I want is to write HW and SW into EPCS16 and,after power on,the system can load SW into sdram from EPCS16,and then run the SW automatically. Now the .sof file .can be written into EPCS16 and work well.But When writing .elf into EPCS16 using IDE's flash programmer the IDE said: No EPCS layout data - looking for section [EPCS-000000] Unable to use EPCS device Leaving target processor paused After searching the Altera's mysupport and forum I found nothing to solve the "[EPCS-000000]" problem,so I tried to use elf2flash to solve it.I did the following: 1) Convert SOF to Flash sof2flash --epcs --input=MyNios.sof --output=hw.flash --quiet 2) Convert ELF to Flash elf2flash --epcs --after=hw.flash --input=MyLed.elf --output=sw.flash --boot=epcs_controller_boot_rom.flash 3) Concatenate cp hw.flash hw_sw.flash cat sw.flash >> hw_sw.flash 4) Create HexFile nios2-elf-objcopy --input-target srec --output-target ihex hw_sw.flash hw_sw.hex  5) Convert hex to jic  quartus ii->file->Convert Programming Files:   Programming file type: JTAG Indirect Configuration File(.jic)  Configuration device: EPCS16  File name: hw_sw.jic  Input files to convert: Flash Loader(EP3C16),Hex_Data(Properties=Absolute addressing,Start Address=0x00000000,hw_sw.hex) Finally the jic file(hw_sw.jic ) was written into epcs using programmer utility of quartus ii by the JTAG connector.Unfortunately the SW did not work while the HW(.sof ffile) worked well.But when "run as hardware" in IDE the SW worked well even though the SW would not work after cycle powering on the board. My questions are: 1. What may be the reason leading to "[EPCS-000000]" ? 2. Is there any person who came across the "[EPCS-000000]" and solved it? 3. Are the above 5 steps correct? Had the SW been written into EPCS16 once the jic was programmed ok? 4. Further more why the SW did not work? Thanks in advance. Liu Jiangning

[Altera_Forum]

Do you have a solution meanwhile? 

May be I can help. I'm using StratixII and EPCS64. With the following commands I programm the EPCS.   # load SOF nios2-configure-sof --cable='USB-Blaster [USB-0]' my_hw_design.sof  # generate EPCS images sof2flash --epcs --input=my_hw_design.sof --output=my_hw_design.flash elf2flash --epcs --after=my_hw_design.flash --input=my_firmware.elf --output=my_firmware.flash  # flash EPCS first with FPGA configuration nios2-flash-programmer --cable='USB-Blaster [USB-0]' --epcs --base=0x21000 my_hw_design.flas  # flash EPCS with Nios firmware nios2-flash-programmer --cable='USB-Blaster [USB-0]' --epcs --base=0x21000 my_firmware.flash  If you do so you didn't need the quartus programmer and conversion of programming files in Quartus.  Cyclone3 has 4 MSEL pins, you set just 0:2 it this correct?  For the [EPCS-000000] problem I have just an idea. Some serial configuration devices (if they not original from Altera) need a description of their structure. Therefore you need a file called "nios2-flash-override.txt" in the C:\altera\72\nios2eds\bin\ directory.  I have attached an examle file for EPCS128.  Jens

[Altera_Forum]

Thank you,Jens.I have solved the problem by my self after added an instance of epcs_controller into top level.

[Altera_Forum]

Hi, LiuJN, 

I have the same problem but I don't know how to solve.  My design has an epcs_controller into sopc and connected to nios.  This controller is connected to fpga signals as decribed in "EPCS Device Controller Core" (Embedded peripherasl document)(DATA0, ASCO, DCLK, FLASH_nCE) but when i try to dowload file with nios2-flash-programmer it fails with "No EPCS layout data - looking for section [EPS-00000]". Can you explain how to you solved your problem? Or anyone can help me? Perhaps do I need extra componets into quartus design? Thanks

[Altera_Forum]

ealonso, which EPCS device do you have? What type of hardware are you using? 

Have you enabled seral configuration in Quartus? For example see the relevant lines in my project .qsf file:  set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE EPCS64 set_global_assignment -name STRATIXII_CONFIGURATION_SCHEME "ACTIVE SERIAL"  Do you specified the correct address? (--epc --base= option in nios2-flash-programmer)  Jens

[Altera_Forum]

Hi Jen, 

I have an EPCS16 connected to Cyclone III. The hardware connection permits both download .sof file via jtag and download .pof file via another connector. The dual port pins are configured initially (pin planner) as: DATA0 - input, DCLK - output, FLASH_nCE-output and ASCO- output.  In 'Device and pin options' it is configured 'Active Serial Standard' and ECPS16 configuration device. I changed 'Dual purpose pins' from 'Input tristate' to 'Regular I/O' as is indicated in the documentation. I connected ecps_controller signals directly to io pins: -input Data0 to data0_to_epcs_controller -sdo_from_epcs_controller to output ASCO -sce_from_epcs_controller to output FLASH_nCE -dclk_from_epcs_controller to output DCLK   I tried to access EPCS by debugging Memory test program in nios eds and it seems tha fail accesing ECPS with the alt_avalon_spi_command, used for reading the EPCS Singnature and EPCS Identifier which are both zero. But accesing via quartus programmer for dowloading the .pof there is no problem.   I don't know if there is anything incompatible with my hardware o if there is anything missing.

[Altera_Forum]

ealonso, I'm using StratixII. For that device I must not assing the EPCS_CONTROLLER signals to pins. 

As I read in the Embedded Peripherals Handbook you have to do that in case of Cyclone3. In Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family (page 9–13) you can see the connection of the EPCS to the FPGA. Futhermore I attached you a example of connection EPCS4 to 3C16. You should also verify the setting of the MSEL pins which selects the configuration schemes. Do you have assigned the correct pin numbers? (see http://www.altera.com/literature/lit-dp.jsp?category=cyc%203&showspreadsheet=y (http://www.altera.com/literature/lit-dp.jsp?category=cyc%203&showspreadsheet=y)  Which Cyclone device you are using?  Jens

[Altera_Forum]

Hi, 

 I'm in the process of fighting the same battle and seem to be having a little more success. I also have a EPCS16 with a Cyclone III.    Everything about how you have your EPCS connected in your design sounds correct. You have the EPCS controller included in your NIOS core. You have the pins connected in the top level and you also set them as user I/O in the device settings. That is all good.    Once I got past all of this I had no trouble using the flash-programmer gui to program both my SOF and ELF files into the EPCS. Though the one thing that did happen to me was that in the GUI I had both file entered in the files fot flash conversion field but had the elf file highlighted. After looking at the output results I noticed that only the elf file was programmed into the flash so be careful about this.   Now my design runs stand-alone. The one thing I can't do is "run as NiosII Hardware" in the NIOS IDE. The NIOS IDE is attempting to load the code into the EPCS and then fails to verify it. I'm guessing I need to somehow get it to load the code into the on-system memory. If anyone has any suggestions on how to fix this, please let me know. Hope this helps.   Lance.

[Altera_Forum]

Hi, again 

 The connections between nios and epcs signals are the same as yours, Jens. And those connectios are ok because we proved them by sending .pof file via jtag, previously transformed into .jic file. (with "file->convert programming files" in quartus ) I think this works someway similar to nios2-flash-programmer but for quartus and fpga files instead nios and firmware files. That's to say, it uses the same signals that i am trying (it load the file via jtag and then it is programmed into epcs via data0, dclk, etc).   We are going to analyze the signals because, if there isn´t anythig else, the problem can be due to bad pull-ups or something like that, relating with these signal after the fgpa configuration fase. (hardware design is not mine, so i dare not change it if i break something).   In other way, i configured the avalon slave clock for the epcs_controlled to 50Mhz (that is my nios frequency). Could it be too fast or is it irrelevant?

[Altera_Forum]

Hi, Lance, 

Have you prove with 'no code at reset' in nios bsp settings? As I've read, the epcs controller loads the reset code automatically into its own on-chip memory and the .text section can be placed at ram. So when you do 'run as..' the .text is placed at ram and the execution starts at '_start', and you don't use epcs. I think it wouldn`t fail.  (I might be wrong, because I haven´t try this yet, but i think it should work this way)

[Altera_Forum]

the epcs_controller clock in my SOPC is the same like NIOS clock (100 MHz). But in case of Cyclone3 I don't know. 

 Here (page 9-12):  http://www.altera.com/literature/hb/cyc3/cyc3_ciii51016.pdf (http://www.altera.com/literature/hb/cyc3/cyc3_ciii51016.pdf)  you can see how pull-ups are used for AS mode. And Table 9-7 (page 9-11) shows the setting of MSEL pins. It should be one of the first 4 modes in the table in your case. You wrote you have 2 connectors one for .sof and one for .pof? Have you connected the right one for flash programmer? I use the JTAG-connector (TMS, TCK, TDI,, TDO) for programming with flash programmer. It is the same on which the .jic file is downloaded.  Jens

[Altera_Forum]

I've got it! 

The problem was not the fpga extra hardware (MSEL and all was ok) nor the epcs_controller in nios.  The problem was the top-level pin assignements in cyclone III. I was using DATA0, DCLK, nCSO and ASCO signals but they weren't well asigned to fpga's configuration pines. Now I can access ecps via nios and i can use flash-programmer. Thank you very much for your help.

[Altera_Forum]

--- Quote Start ---  Have you prove with 'no code at reset' in nios bsp settings?  --- Quote End ---     Thanks for the advice. It worked.

[Altera_Forum]

ealonso, 

 I'm struggling with this same problem.  Can you be a bit more specific on your May 6th post? When you write "weren't well asigned to fpga's configuration pines" what do you mean? Do you mean weren't assigned correctly? What assignment did you end up with?  I have DCLK assigned to pin 12, Data0 assigned to pin 13, nCSO (named sce in the VHDL model) assigned to pin 8, and ASCO (named sco in the vhdl model) assigned to pin 6.  Thank you for your help so far

[Altera_Forum]

@ttrickel 

 I believe what ealonso meant was that, after he instantiated the epcs_controller inside his FPGA, he has to connect the epcs_controller signals to the top level of his FPGA. He then has to assign those top level FPGA ports to pins using the Pin Planner. He probably meant he wasn't assigning them properly in the Pin Planner.     Please refer to page 4-3 in Embedded Peripherals IP Users Guide for more information of these steps.