Fails to compile when using the hard DDR controller in Cyclone V part.

[Altera_Forum]

HI, 

 I am using the Altera Cyclone V GT development kit. I have been working with this board for about 2 years.   The card has 2 banks of DDR memory. One bank is 64-bits wide, and uses a soft core. The other bank is 32-bits wide and uses a hard core. I have been using the 64-bit memory.  I have a need to add the 32-bit memory to the mix. I added the 32-bit core to my design. I am getting a fail at compile time. The failure message is shown below. Does anyone know what this message means, and how I can fix it?  Error (17044): Illegal connection on I/O input buffer primitive ADC_Block :U1|q_sys_all :b2v_inst10|q_sys_all_DDR3_VRB :ddr3_vrb|q_sys_all_DDR3_VRB_p0 :p0|q_sys_all_DDR3_VRB_p0_acv_hard_memphy:umemphy|q_sys_all_DDR3_VRB_p0_acv_hard_io_pads :uio_pads|q_sys_all_DDR3_VRB_p0_altdqdqs:dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev :altdq_dqs2_inst|strobe_in.  Source I/O pin ADC_Block:U1|q_sys_all:b2v_inst10|q_sys_all_DDR3_VRB:ddr3_vrb|q_sys_all_DDR3_VRB_p0 :p0|q_sys_all_DDR3_VRB_p0_acv_hard_memphy:umemphy|q_sys_all_DDR3_VRB_p0_acv_hard_io_pads :uio_pads|q_sys_all_DDR3_VRB_p0_altdqdqs:dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev :altdq_dqs2_inst|obuf_os_0 drives out to destinations other than the specified I/O input buffer primitive.  Modify your design so the specified source I/O pin drives only the specified I/O input buffer primitive.  File: C:/Echodyne/FPGA_Files/A_Current_Files/ADC_Card5_S8_Vector_LB/Q_SYS_ALL/Q_SYS_ALL/synthesis/submodules/altdq_dqs2_acv_connect_to_hard_phy_cyclonev.sv Line: 954

[Altera_Forum]

HI, 

 The error message looks like you are connecting Hard DDR pin to your own user design.  Hard DDR controller UNIPHY IP comes with dedicated hard pin connection. You can't connect hard DDR pin to your user design. It's only allow to connect to external SDRAM on board.   Thanks.  Regards, spdl2001 (This message was posted on behalf of Intel Corporation)