Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
20872 Discussions

Failure Analysis on MAX10 FPGA

Pat2
Beginner
321 Views

We have a customer field return, and the failure was isolated to to a bad clock output from pin N4 onthe MAX10 (196 UBGA).  This is a singular failure, not a widespread issue, but it is a field return on a unit that previously passed all tests.  We suspect the MAX10 was damaged somehow, or may have a latent defect.  Can we get failure analysis on this device, please?

 

I work for Infinera, and our board CM is Jabil.

 

Thanks,

Pat

0 Kudos
1 Reply
Zawani_M_Intel
Employee
291 Views

Dear Pat2,

 

Thank you for using Intel FPGA Community Forum.

We have sent you a private email to continue support your FA request.

Thank you. Have a great day!

 

Wani

0 Kudos
Reply