Hello everyone. I am currently working with a transceiver design project using Stratix V GT (5SGTMC7N). However, I have no experience with transceiver design (I only have some basic knowledge about verilog and FPGA). What I am planning to do is building a simple link via the GXB SMA connectors. Then I want to start a really low speed communication using push button as input method, so I write some assignment instructions like: assign GXB_TX_L11n = USER_PB. There is a compilation error said that I cannot connect general user input to on-chip terminal. Does this mean that I have to use IP cores to implement any transceiver designs? Or is there any way that I can fix this error and make a such design without using IP cores?If the IP cores is necessary to my design, how can I get started? I read some altera wikis and went through some design examples but I still have no ideas about how to use IP cores. Thanks in advance.
Yes, transceiver dedicated input and output pins must be connected to transceiver PHY IP Cores such as Stratix V Native PHY IP Core. You can find the IP core in IP catalog tool in Quartus II software. I recommend the design flow on alterawiki.com as your first step.http://www.alterawiki.com/wiki/transceiver_design_flow You may see a GUI called MegaWizard in the design flow, but Altera has terminated MegaWizard tool. IP catalog is the replacement. No worry, look and feel are almost same as MegaWizard. One thing you need to be noted is that the transceiver has minimum data rate spec (660 Mbps, 1G bps etc.). Check the datasheet for your target device.