Flex 6000 clock gating

[Altera_Forum]

Hi 

 I've been converting a 10 year old non-synchronous design to make synchronous so that it is more robust. Due to the available clocks on the board, it is necessary to use a gated clock. The old design implemented this using logic cell delays making the design non-portable through different design software versions.  I have used the recommended Altera gating method as described in the Quartus II handbook "Recommended Clock-Gating Methods" chapter (attached clock_gate.jpg), but this does not work without glitches on Flex 6000 speed grade 1 devices in simulation. It does work with for example MAXII devices, or Flex 6000 speed 2 or 3.  I have attached a block design file showing the design for both rising and falling edge clocks together with the simulator (waveform) output in the zip file, compiled with Quartus II v7.2. Also provided the design as a jpeg (gate_design.jpg) and simulation (simulation.jpg).  Interestingly, if I swap the AND and OR gates the design works without glitch, so it looks like there is a delay on the global clock reaching the AND/OR gates causing the glitch. Any ideas on resolving this?  Cheers  Gordon

[Altera_Forum]

--- Quote Start ---  Hi  I've been converting a 10 year old non-synchronous design to make synchronous so that it is more robust. Due to the available clocks on the board, it is necessary to use a gated clock. The old design implemented this using logic cell delays making the design non-portable through different design software versions.  I have used the recommended Altera gating method as described in the Quartus II handbook "Recommended Clock-Gating Methods" chapter (attached clock_gate.jpg), but this does not work without glitches on Flex 6000 speed grade 1 devices in simulation. It does work with for example MAXII devices, or Flex 6000 speed 2 or 3.  I have attached a block design file showing the design for both rising and falling edge clocks together with the simulator (waveform) output in the zip file, compiled with Quartus II v7.2. Also provided the design as a jpeg (gate_design.jpg) and simulation (simulation.jpg).  Interestingly, if I swap the AND and OR gates the design works without glitch, so it looks like there is a delay on the global clock reaching the AND/OR gates causing the glitch. Any ideas on resolving this?  Cheers  Gordon  --- Quote End ---    Hi,  why are you trying to use clock gating ? Is it not possible for you to use the signal called "enable" as enable for your register ?  Kind regards  GPK

[Altera_Forum]

Hi,  

 do you have to provide those gated clocks to external circuits? Or will they be used only within the FPGA? If the later, I recomend that instead of clock gating, you design with clock enables.

[Altera_Forum]

The gated clock is going only to a pin on the device for an external circuit, and clocks nothing internally. The clock in this legacy design is not fast enough to achieve the external data transfer without a gated clock. I have to change the contents of a data bus every clock cycle, and provide a negative going pulse, midway between data bus changes to transfer the data. Data is not transferred on every clock cycle though, so the pulse needs not to be present some of the time. 

 I have found now that the gating circuit operates correctly for speed grade 2 (which the design uses) and 3 Flex 6000 devices. I still don't get why the speed grade 1 devices glitch though.  Cheers  Gordon

[Altera_Forum]

Quite curious indeed. 

I'd go and look at the postfitting netlist for -1 and -2 speed grades. I'd also go and take a look at the waveforms for the pins of the LEs involved.  From there, you might be able to work arround the issue by placing a delay LCELL somewhere in the design.

[Altera_Forum]

--- Quote Start ---  The gated clock is going only to a pin on the device for an external circuit, and clocks nothing internally. The clock in this legacy design is not fast enough to achieve the external data transfer without a gated clock. I have to change the contents of a data bus every clock cycle, and provide a negative going pulse, midway between data bus changes to transfer the data. Data is not transferred on every clock cycle though, so the pulse needs not to be present some of the time.  I have found now that the gating circuit operates correctly for speed grade 2 (which the design uses) and 3 Flex 6000 devices. I still don't get why the speed grade 1 devices glitch though.  Cheers  Gordon  --- Quote End ---    Hi,  you have to keep in mind that the speed of an FPGA shows a large varation depending on the temperatur, power supply and the process of production. That means you can not be sure that your design will run with all speed grade 2 devices. If you only need one of your boards it is maybe ok, but you should not use it for a production.   Kind regards  GPK