Because the pin resources in the design is limited, we need 3A and 3B BANK IO voltage is 1.8V using the 5sgxma4k2f40c3n FPGA, and is limited by the power consumption the SPI Flash is 1.8V SPI Flash.So I use the following configuration scheme,
BANK3AB power supply situation: VCCIO3A/VCCIO3B=1.8V ,VCCPD3AB=2.5V, VCCPGM=1.8V
Using SPI X4 configuration mode, SPI Flash IO voltage is 1.8V level.
JTAG pull-up voltage is 2.5V.
This configuration scheme can work?
TKS!
