Function of Pin L2 in Max10 U169 package (10M16SAU169)?

[Altera_Forum]

Does anyone know the function of pins L2 N12 L13 C13 A5 on the MAX 10 U169 package? (e.g. part# 10M16SAU169) 

 Altera's pin description files leave the associated lines essentially blank. The Quartus pin planner shows them as a 'D' with a circle around it, but I don't know what that means either, and there are other pins with actual names (JTAGEN, CONFIG_SEL) with the same symbol.  In particular I am trying to do a PCB layout and would like to know whether they can be connected to VCC, or ground, or used as an IO. Or is there another function?

[Altera_Forum]

The Pin Planner and pinout files are pretty clear about these pins. They are regular IOs without optional function.

[Altera_Forum]

This is not obvious, at least to me. In the "pinout planner" GUI, the graphical representation of these pins is a 'D' with a circle in it. The only other pins with this symbol are special configuration pins, which have constraints on what can be connected to them when the FPGA is powering on.  

  The pin legend (View | Pin Legend Window) indicates that these are "other dual purpose pins". So given the mystery function, does anyone have experience connecting these pins to a supply rail?

[Altera_Forum]

Unfortunately I can't tell you what the "D" in Pin Planner exactly means, but MAX10 has no "Dual Purpose Pins" like other FPGAs because it doesn't use external configuration memory. 

 Your first source of information about pin functions should be the Pinout File of the respective device, it shows that the said pins are regular IO pins without optional function.  I don't understand why you would connect the pins to a supply rail? According to the default configuration of unused pins as tri-stated with weak pull-up, you'll leave it unconnected.

[Altera_Forum]

OK, thanks very much for your help. After reading through the documentation I still have not found these pins mentioned anywhere but the mostly blank lines in the pinout files; maybe the designers have some kind of future migration in mind. As you suggest, Quartus does allow defining them as IO. 

 In a possibly misguided and maybe ultimately futile attempt to do the layout on a 2-layer board, I am running several lines across unused pins on the top layer so as to maintain ground continuity on the bottom. It is a challenge, at any rate.