Graphic controller with DDR2 and LVDS on EP4CE6

[ProgAddicted]

I still working on a redesign of an old working graphic card with STM32 (FSMC interface), CycloneIII, SDRAM (frame memory), LVDS interface to 124x768 display.

Cyclone is no more supported, so i have decided to move to CycloneIV family and to DDR2 as frame memory.

In the previous revision i didn't pay any attention to the pin assignment for SDRAM interface and now with the new design i receive some critical warnings.

Is there a design example (schematic) to interfacing CycloneIV with DDR2?

In CycloneIV Handbook Table 7-2 shows Device DQS and DQ Bus Mode Support; my memory is x32. It's possible to connect x32 DDR2 to EP4CE6 using two x16 Groups, Bottom and Top?

Best regards, Lorenzo.

[AdzimZM_Intel]

Hi Lorenzo,

"In CycloneIV Handbook Table 7-2 shows Device DQS and DQ Bus Mode Support; my memory is x32. It's possible to connect x32 DDR2 to EP4CE6 using two x16 Groups, Bottom and Top?"

• Yes, it's possible but in x8 DQ group instead

Regards,

Adzim

[ProgAddicted]

Thank you for your response. I still have a few more questions.

The actual FPGA is Cyclone III and the memory a PSRAM. The new version must drive a double LVDS display (1920x720). Cyclone III is no longer supported and Cyclone III and IV were removed from "External Memory Interface Handbook" in 2013. For this reason i chose Cyclone V E (i don't need ..), F484 or U484.
My questions:
1) Is it possible to control one DDR2 x32 chip using 2 Top x8 groups and 2 Bottom x8 groups?
2) My DDR2 run at 200 MHz, it is fair to say that it is enough to use 4 x8 groups and Soft Memory Controller, so can i use 4 x8 Bottom groups of a Cyclone V E A2 UBGA484 or FBGA484 or MBGA383?
3) Apart from speed, are there any other parameters that differentiate Soft Memory Controller from Hard Memory Controller?
4) Is there an example of an application of a DDR2 memory controller without the NIOS?

Grazie per ogni risposta.

[AdzimZM_Intel]

Hi Lorenzo,

"1) Is it possible to control one DDR2 x32 chip using 2 Top x8 groups and 2 Bottom x8 groups?"

• Yes but it's has a high latency

"2) My DDR2 run at 200 MHz, it is fair to say that it is enough to use 4 x8 groups and Soft Memory Controller, so can i use 4 x8 Bottom groups of a Cyclone V E A2 UBGA484 or FBGA484 or MBGA383?"

• Yes, it's depend on the data width.

"3) Apart from speed, are there any other parameters that differentiate Soft Memory Controller from Hard Memory Controller?"

• Usually the soft memory controller will use the soft logic instead of harden logic.
• I think you will need to have your own memory controller for the soft logic.

"4) Is there an example of an application of a DDR2 memory controller without the NIOS?"

• You can here: https://www.intel.com/content/www/us/en/support/programmable/support-resources/design-examples/design-store.html?f:guidetm83741EA404664A899395C861EDA3D38B=%5BIntel%C2%AE%20Cyclone%C2%AE%3BCyclone%C2%AE%20V%20FPGAs%20and%20SoC%20FPGAs%5D&f:guidetm5203BAD641A146288EA061D522BFD990=%5BMemory%20Interfaces%20and%20Controllers%5D
• The example design with DDR2 memory IP may already EOL, thus the design may not available if you cannot find it in the design store.

Regards,

Adzim

[AdzimZM_Intel]

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