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Help!! need help for VHDL car detect system.

Altera_Forum
Honored Contributor II
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hey guys, i'm new with vhdl and i have to write the following programm, and i need help. 

 

1.To detect number of car. 

2.output s is the current number of car. 

3.output a is the previous number of car. 

4.to load the the previous number of car into the system when an active-low load input is activated. 

5.led to light when 64 cars is detected. 

 

I have problem on the load part so i hope u guys can enlighten me. below are some parts i have done. Thanks:) 

 

library ieee; 

use ieee.std_logic_1164.all; 

use ieee.numeric_std.all; 

entity project is 

port ( sensor : in std_logic; 

reset : in std_logic; 

load : in bit; 

s : out std_logic_vector (5 downto 0); --current number 

a : out std_logic_vector (5 downto 0); -- previous number 

led_on : out bit); 

 

end project; 

 

architecture flow of project is 

signal count_sig: unsigned (5 downto 0); 

begin 

process (sensor, reset, load) 

begin 

if (reset='1') then 

count_sig <= "000000"; 

 

elsif rising_edge (sensor) then 

count_sig <= count_sig+1; 

 

end if; 

end process; 

s <= std_logic_vector (count_sig); 

end flow;
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Altera_Forum
Honored Contributor II
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usually, you can just store it in an internal register: 

 

if load = '0' then 

a <= count_sig; 

end if; 

 

or some other stored version of count_sig. 

 

I am concerned you are not using a real clock. Using an input as a clock (by looking for the rising_edge. can cause timing problems.
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Altera_Forum
Honored Contributor II
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thanks..i will try it but can elaborate more on the clock cause i dont really understand.

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Altera_Forum
Honored Contributor II
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hey i hv error after trying tat.. 

"Error (10476):type of identifier "count_sig" does not agree with its usage as "std_logic_vector" type" 

what does this error mean?? 

thanks
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