High-Speed Source-Synchronous Differential I/O Interfaces in Cyclone 10 GX Devices

[Altera_Forum]

background:  

My end goal is to implement source synchronous differential IO interface with Cyclone 10 GX devices : 4 data lanes with 1 clock line at 2.5 Gbps with 1.25 GHz.  Cylone 10 GX devices has dedicated LVDS lines with HARD IP Serializer and Deserializer which allow LVDS at 1.434 Gbps. This is a limitation in my application. I am trying to use transceivers for 2.5 Gbps instead of LVDS IO resources.    question:  I am looking for a document or a design example or a reference design for High-Speed Source-Synchronous Differential I/O Interfaces in Cylone 10 GX Devices.    extra information:  For other current GX devices, it is also fine.   I found the following document published at 2006. I am looking for a updated version of it.   https://www.altera.com/en_us/pdfs/literature/hb/sgx/sgx_sgx52013.pdf

[Altera_Forum]

Hi, 

 Refer session 5.2 of the handbook. https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/hb/cyclone-10/c10gx-51003.pdf  Let me know if this has helped resolve the issue you are facing or if you need any further assistance.  Best Regards, Anand Raj Shankar (This message was posted on behalf of Intel Corporation)

[Altera_Forum]

Hi, 

 You can find reference designs for Cyclone10 GX here:  https://cloud.altera.com/devstore/platform/?acds_version=any&family=cyclone-10-gx&board=102  You can find the Cyclone10 GX transceiver guide here:  https://www.altera.com/documentation/hki1486507600636.html  https://www.altera.com/products/fpga/cyclone-series/cyclone-10/cyclone-10-gx/support.html  statix10 lvds guide : [url]https://www.altera.com/documentation/sam1439794388346.html (https://www.altera.com/products/fpga/cyclone-series/cyclone-10/cyclone-10-gx/support.html)  http://www.alterawiki.com/wiki/high_speed_transceiver_demo_designs_for_current_and_older_families  http://www.alterawiki.com/wiki/source_synchronous_interfaces_between_altera_fpgas [/URL]