How can I make comunication between dsp and Dual-Port Ram internal FPGA?

[Altera_Forum]

I want to comunicate dsp with Dual-Port Ram internal FPGA.Because there are two Dual-Port Ram in FPGA, and one to read,the other one to write.Now the databus is bidirectional,so I must transform the bidirecional databus to two bus,the one is in,other one is out. 

I have tried and emulated ,but it didn't work correctly.the databus (DATA1 )output allways keep "XXXX". Thank you for any help!   This is the code:   library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; ENTITY busTrans IS PORT ( RESET :IN STD_LOGIC;  VMECS_N :IN STD_LOGIC; WRITE :IN STD_LOGIC; READ :IN STD_LOGIC; ADDRESS :IN STD_LOGIC_VECTOR(11 DOWNTO 0);  DATAbus :INOUT STD_LOGIC_VECTOR(23 DOWNTO 0); DATA1 :OUT STD_LOGIC_VECTOR(15 DOWNTO 0); DATA2 :IN STD_LOGIC_VECTOR(15 DOWNTO 0);  ------other RAM1EN :OUT STD_LOGIC ;--ram1 enable  IOCS_N :OUT STD_LOGIC  ); END busTrans; ARCHITECTURE a OF busTrans IS BEGIN --begin ARCHITECTURE p1: PROCESS (RESET,VMECS_N,ADDRESS,DATAbus,DATA2) BEGIN --begin process if(RESET='1') then IOCS_N <='1';  elsif(VMECS_N='0') then -- IOCS_N <='0'; -- if(ADDRESS(11 downto 6)= "000000") then  RAM1EN<='1'; DATA1(15 DOWNTO 0)<=DATAbus(15 DOWNTO 0); elsif(ADDRESS(11 downto 6)= "000001") then  RAM1EN<='0'; DATAbus(15 DOWNTO 0)<=DATA2(15 DOWNTO 0); end if; else RAM1EN<='0';  end if;   END PROCESS p1; END a;

[Altera_Forum]

In your process (Which is an Asynchronous process) the signals DATAbus and Data1 and IOCS_N are not assigned on all paths though the logic. This will infer storage (Latches). I imagine this is not what you intend.  

 i.e. what is the value of RAM1EN when Address is all ones?   I suggest you either rewrite your code as a synchronous process or if you just want combinatorial logic then ensure all signals are assigned in all paths

[Altera_Forum]

Thank you very much! 

I will rewrite my code.