How much of a cache's cost is taken up in being able to read to it from a bus and write from it to a bus? If that ability were taken away, what would be the cost as a percentage of the original cost? I'm wondering how expensive it would be to completely get rid of the address bus and the data bus, and convert a cache into a giant shift register, its performance depending on one bit; if the bit was low, each byte in the cache would stay right where it was; if the bit was high, each byte would write its value into the byte that's just higher in some order. The input to the cache would go into the byte that was lowest in the order, if that control bit was high. The output from the cache would be the contents of the byte highest in that order. How much would this cost relative to typical caches in use today?
The whole point of a cache memory is to provide very low latency (ie, one clock cycle) random access to a small set of locations. Your architecture does not do that. It appears you are describing something more like a FIFO with a write enable input.