How to access the QSPI flash in PS mode?

[Rainwang]

hi, 

We have a MT25QU01G device connected to A10 FPGA via the Dedicated Active Serial Interface pins.

ususally we used the flash as AS config flash for the FPGA configuration and it works well.

In another scenario, we make the FPGA work on PS mode and the HPS will configure it. At this time, the flash MT25QU01G for FPGA AS configuration is no use and we want to use it as a general memory to store some user data in it.

in the platform designer, we use a Generic serial flash interface(GSFI) IP to access the flash. The flash can be accesssed without issue when the FPGA is configured with AS mode.

but when we config the FPGA with PS mode, the HPS can't access the flash successfully via the GSFI IP.

so my questions:

How Can I access the flash connected to Dedicated Active Serial Interface when FPGA configured in PS mode? or it is impossible? please give me your proposal, thank you!

[Farabi]

Hello, 

You may want to refer here: https://www.intel.com/content/www/us/en/docs/programmable/683419/24-1-20-2-5/flash-access-using-the.html

regards,
Farabi

[Rainwang]

hi, 

I have already has this document on my hand and as I mentioned, I can access the flash successfully when I set the FPGA as the AS mode.

Now i need to access the flash when the FPGA was configured with PS mode. but it seems the GSFI IP can't work normally when the MSEL were set to PS mode.

For example,  as below figure shows, when i tried to read the device ID on PS mode, it will be read as the "0xFFFFFFFF", but when i set the FPGA to AS, the device ID can be read out successfully.

So my question:  how can my HPS access the flash(which is connected to FPGA dedicated pins, not general pins) when the FPGA was configured with PS mode?

thanks.

[Rainwang]

I also noticed some notes in the document as below:

Note: To access the AS configuration flash, set the MSEL pins of the FPGA devices to the AS configuration mode. To access the general purpose QSPI flash, enable the Disable Dedicated Active Serial Interface and Enable SPI Pins Interface parameter of this IP.

As I mentioned, our serial flash are connected to dedicated pins of CSS bank on Arria 10.  you can refer to the red highlighted in below figure.

our board works on AS mode without issue, and we can access the serial flash to update the app image in system, this feature was realized.

In other scenario, we need the board work on PS mode. HPS boot first then configure the FPGA, and then we need to use the serial flash to  store some user data. 

But the serial flash is physically connected to the FPGA dedicated pins so I don't know if we can access it in PS mode. 

[Fakhrul]

Hi Rainwang,

Please refer to this document for more clarity on utilizing the QSPI guidelines: QSPI Flash Interface Design Guidelines.

Best regards,

Fakhrul

[Rainwang]

hi, Fakhrul

I just checked the link you provided, it is not for my scenario. 

We have 2 QSPI flashes connected to A10.

the 1st one is connected to the HPS dedicated pins and is used for the HPS boot from QSPI. it contains the SPL/uboot image and the OS image and also our app.

the 2nd one is connected to the FPGA dedicated pins and is used for the FPGA AS mode configuration. it contains the FPGA image which we programmed into it via the *.JIC file.

so in this case the HPS boot from 1st QSPI and the FPGA configured from the 2nd QSPI seperaterly and both work well so far.

but in other situation, we need the 2nd QSPI to store some user data.

so we changed the booting mode.  we also added the FPGA image file into the 1st QSPI flash. the HPS will boot firstly then configure the FPGA in PS mode during SPL/uboot stage and then the OS and app will boot. in this mode, both the HPS and FPGA images will only be stored in the 1st QSPI, the 2nd  will be used as user data storage device.

but we found in this case we can't access the 2nd QSPI flash. 

this is our question. 

expect your prompt response.

thank you.

[Fakhrul]

Hi,

Based on your description, the issue with accessing the second QSPI flash may be due to:

• FPGA Retaining Control: Ensure the FPGA design releases the second QSPI after configuration in PS mode.
• Software Initialization: Verify that SPL/U-Boot initializes the second QSPI correctly for data storage and that the device tree or address mapping reflects the changes.
• Pin and Clock Conflicts: Check for conflicts or misconfigurations in the QSPI pin assignments and clock settings.

You can debug by testing low-level access to the second QSPI and enabling logs in SPL/U-Boot or Linux. Let me know if further assistance is needed!

Best regards,

Fakhrul

[Rainwang]

thanks for the reply.

please see my answer below.

• FPGA Retaining Control: Ensure the FPGA design releases the second QSPI after configuration in PS mode.(we can access the QSPI device successfully  after FPGA AS configuration. for PS mode, the device doesn't work as a config device, so i don't think FPGA will still occupy this device. Or, can you tell me how to verify this?)
• Software Initialization: Verify that SPL/U-Boot initializes the second QSPI correctly for data storage and that the device tree or address mapping reflects the changes.(as i mentioned above, we can access the QSPI device successfully  after FPGA AS configuration, we use the same SPL/U-boot when we try to access the device after PS configuration.)
• Pin and Clock Conflicts: Check for conflicts or misconfigurations in the QSPI pin assignments and clock settings.(since we can access the device after AS configuration, it can be verified that no pin or clock related error.)

thanks.

[Fakhrul]

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