1st Quartus cannot fit customers timing constrain condition. *as showcased in file*
2nd, Arria 10 cannot fit the timing internally inside FPGA (from DDIO IP output to registers). We checked the previous version of this IP. The IP will output data at positive edge of the clock. But now in version 18.1, the data will be output at negative edge of the clock. That means the setup condition is more strict.
How can the engineers address? please review file.
Can you please provide an email address to share the project files with and without PLL directly?