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How to address two sperate timing constraints in the Arria 10 IO to drive ADC3224 chip (100MSPS)

JoelCaruso
Employee
242 Views

1st Quartus cannot fit customers timing constrain condition. *as showcased in file*

2nd, Arria 10 cannot fit the timing internally inside FPGA (from DDIO IP output to registers). We checked the previous version of this IP. The IP will output data at positive edge of the clock. But now in version 18.1, the data will be output at negative edge of the clock. That means the setup condition is more strict.  

 

How can the engineers address? please review file.

 

Can you please provide an email address to share the project files with and without PLL directly?

 

0 Kudos
3 Replies
KhaiChein_Y_Intel
140 Views

Hi,

 

I have sent an email to you. Please let me know if you do not receive.

 

Thanks.

Best regards,

KhaiY

KhaiChein_Y_Intel
140 Views

Hi,

 

Do you have any updates?

 

Thanks.

Best regards,

KhaiY

JoelCaruso
Employee
140 Views

Hi KhaiY - didn't see your email direct to me, however this issue was addressed by a FAE and solved. The answer was to use PHY Lite for Parallel Interfaces Intel FPGA IP a free IP. Which would perform at a higher frequency than GPIO.

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