I asked "Is it possible to see how many BUFG by using Quartus software?" in https://community.intel.com/t5/Programmable-Devices/About-the-BUFG-specification-in-Intel-FPGA/m-p/1438749 , and got the answer: Quartus compilation report tells which resources are utilized for specific signals. Generally, it's rarely necessary or even useful to assign clock resources, e.g. clock control blocks in a design manually.
Thanks for that, however, I am still not clearly about it, is there a demo design that assigned clock resources, e.g. clock control blocks manually? I need to check if the Quartus compilation report tells the usage of GCLK resources. Or the compilation report can't tells it?
There is a Global Signals report in the Compilation Report which is probably what you are looking for. I forget where it is (don't have Quartus open presently), but it's there.
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