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Hello,
Is there a description and example for connecting 2 DDR3 interfaces to FPGA ?
Thank you,
Ran
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Hi,
If you are using Arria 10 FPGA, refer to the below document
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-20115.pdf page 38, "2.6. Hardware Resource Sharing Among Multiple EMIFs " and "Figure 17. I/O Bank Sharing "
Similarly, there should be documents for other FPGAs.
https://www.intel.com/content/www/us/en/programmable/support/literature/lit-external-memory-interface.html
With Regards,
HPB
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Hi,
If you are using Arria 10 FPGA, refer to the below document
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-20115.pdf page 38, "2.6. Hardware Resource Sharing Among Multiple EMIFs " and "Figure 17. I/O Bank Sharing "
Similarly, there should be documents for other FPGAs.
https://www.intel.com/content/www/us/en/programmable/support/literature/lit-external-memory-interface.html
With Regards,
HPB

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