How to create IP from a multy-library vhdl project in Quartus.

[Artak]

I have a Quartus vhdl project consisting of about 10 vhdl libraries and about 150 vhdl files.

Would like to create an IP from it in order to instantiate to a bigger design.

The same project for xilinx FPGAs is being  easily encapsulated into IP by "Create and package IP" command in Vivado .

Could not find an similar functionality with Qsys/Platform designer (e.g. to read the project qpf file instead of manually specifying all the files). And could not find a way to group files in libraries while adding them to Qsys project. 

The library pragma is not supported since it is Quartus Pro

Is there any practical way to do it?

[sstrell · Accepted solution]

Since you're using Pro, probably the best solution would be to use the core reuse developer flow to create a .qdb file.  Documentation here: https://www.intel.com/content/www/us/en/docs/programmable/683247/19-4/block-based-design-flows.html.  Training here: https://cdrdv2.intel.com/v1/dl/getContent/652869?explicitVersion=true.

[Nurina]

Hello,

Does the above reply answer your question?

Regards,

Nurina

[Artak]

Hi Nurina,

Yes it answers my question

[Nurina]

Hello,

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

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Regards,

Nurina