How to create SPI slave in FPGA when SCLK frequency is of order comparable to FPGA system clock?

[gyuunyuu]

I need to design an SPI slave peripheral inside an FPGA that shall be used to communicate with a Microcontroller and configure the behaviour of the FPGA design. I have a few questions.

1. If the FPGA clock frequency is significantly higher than the input SCLK frequency, it is possible to sample the SCLK and detect the rising and falling edges. The design can use this information to shift or latch data. But, (a) What if the SCLK input clock is almost of same order as the FPGA system clock? Does the clock signal connect directly into the FPGA registers? (b) If not then what is the alternative?I am in this situation where the FPGA system clock is not 4 times or more than the SCLK frequency. 

2. If (a) above is true then how do we write the timing constraints?

3. The SCLK does not need to use global clock routing. Does this mean that any FPGA pin can be used for it?

How should such a slave be designed, and timing constrained and work in reliable way?

[EngWei_O_Intel]

Hi there

Are you using the SPI IP from Quartus tools? You can refer to the SPI IP spec in the doc below:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_embedded_ip.pdf

There are also some design examples available in the link below where you can refer to the connection:

https://fpgacloud.intel.com/devstore/platform/?search=spi&acds_version=any

thanks.

Eng Wei

[gyuunyuu]

The UG-01085 states:

5.3.1.2. SPI Clock (sclk) Rate
This setting determines the rate of the sclk signal that synchronizes data between
master and slaves. The target clock rate can be specified in units of Hz, kHz or MHz.
The SPI master core uses the Avalon-MM system clock and a clock divisor to generate
sclk.

The actual frequency of sclk may not exactly match the desired target clock rate.
The achievable clock values are:

<Avalon-MM system clock frequency> / [2, 4, 6, 8, ...]
The actual frequency achieved will not be greater than the specified target value.

It looks like the SPI slave has been designed in the normal way and not where the SCLK clock is used to clock the FPGA registers. There does not seem to be an easy way out of this at all.

[EngWei_O_Intel]

It is design dependent whether the the clock signal is to connect to the registers. If SCLK is going to clock network, we shall connect it to clock pin.

I am from IO team and might not be the best person to comment on SPI design and usage. If there is any Avalon specific question, I suggest you to file another question and someone will be able to provide support on it. 

Thanks.

Eng Wei

[EngWei_O_Intel]

This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

[茫于000]

SCLK的频率无论是多少，我都会用PLL输出SCLK的8倍左右，通过锁定SCLK的上升沿和下降沿来输出MOSI或者MISO。另外还需要考虑FPGA和其他器件的主从关系，一般来说，MISO需要重点关注其他器件的数据的建立时间和保持时间（从其他器件的手册上获取），根据这个来算得PLL到底需要输出多少频率的时钟来采样。

[gyuunyuu]

すみません。わかりません。英語で説明してください。