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I want to merge a module and the related submodules files I created in one project into another project. But the issue is that there are not only pure Verilog HDL files. Some of the files in the project to be exported are using Altera IPs. So even if I copy and pasted these files in the other project how do I export the IPs as well?
Any help is most appreciated.Link Copied
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to copy a MegaCore function, the easiest way may be to copy the variation .v/.vhd into the new project, open the variation in the MegaWizard, then select the variation, and regenerate the core
alternatively you could gather all of the files named <variation_name>.* and the associated libraries (they should have obvious names like fir_compiler-library) and copy them to the new project directory. add the copied <variation_name>.qip to the new project and you should be good to go (newer .qip files use relative paths) i use a script to create .qip files for my own HDL to make the process easier
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