How to find largest value and its position in memory array?

[Altera_Forum]

As attachment... the memory array contains continuous input at every positive edge clock... these inputs are the outputs from the Altera FFT core... then i need to find the peak and its location... please help!!! thanks alot! from the attachment, the peak should be 45 and at memory_array [2].... and they should be shown at the outputs...

[Altera_Forum]

--- Quote Start ---  you don't need to push fft output forward. All you need is check the fft frame when ready for peaks. The location of peak need to be adjusted for latency issues so you need to check that in simulation.  For multiple peaks you shouldn't use max value, instead you need to define an absolute threshold to define your peaks then check fft output against that threshold, save peaks accordingly.  --- Quote End ---    ok i'll try... hope i can do it... thanks!

[Altera_Forum]

let say now i set the threshold as 1000000, and above this value, the peak values and their locations will be outputted in a single waveform as shown in the attached picture, and how to save each peak value and location in different registers for me to do further calculations?

[Altera_Forum]

--- Quote Start ---  let say now i set the threshold as 1000000, and above this value, the peak values and their locations will be outputted in a single waveform as shown in the attached picture, and how to save each peak value and location in different registers for me to do further calculations?  --- Quote End ---    run a counter enabled only when a peak occurs. so you then save peak0 at count0 into reg[0] then save peak1 at count1 into reg[1] and so on.

[Altera_Forum]

--- Quote Start ---  run a counter enabled only when a peak occurs. so you then save peak0 at count0 into reg[0] then save peak1 at count1 into reg[1] and so on.  --- Quote End ---    is it like this?  reg [26:0] peak_value [0:10]; reg [14:0] peak_location [0:10];  reg [3:0] i;  always @ (posedge clk)  begin   if (data_en)   begin  if (abs_source_real > peak_value_temp)  begin  peak_value <= abs_source_real;  peak_location <= Q-3;  end  Q <= Q + 1;  i <= i + 1;    end   end

[Altera_Forum]

--- Quote Start ---  is it like this?  reg [26:0] peak_value [0:10]; reg [14:0] peak_location [0:10];  reg [3:0] i;  always @ (posedge clk)  begin   if (data_en)   begin  if (abs_source_real > peak_value_temp)  begin  peak_value <= abs_source_real;  peak_location <= Q-3;  end  Q <= Q + 1;  i <= i + 1;    end   end  --- Quote End ---    No, I said increment counter i only when a peak occurs. So put inside your test construct, not outside as it will keep going up and becomes same as Q

[Altera_Forum]

--- Quote Start ---  now i change to these codes and the output as shown in picture attachment...   input wire Enable;  input wire [9:0] d_in; output reg [9:0] max_value; output reg [2:0] max_location;   reg [2:0] Q;   initial  begin  max_value = 0;  end   always @ (posedge clock)  begin   if (Enable)   begin    if (d_in > max_value)  begin  max_value <= d_in;  max_location <= Q;  end  Q <= Q + 1;  end   end  endmodule  --- Quote End ---   hi GOH WEN SHIN.. i have similar as u..      down votefavorite (http://stackoverflow.com/questions/37365944/verilog-code-to-find-max-and-min-value-in-an-input?noredirect=1#)   I want to find max and min in input file, read from a memory. This input file size 1000 decimal sample values. I have written the following code to find max and min by comparing with a threshold.  module max_min(input clk, input [15:0]din, output [15:0]dout); reg [15:0]max=0; reg [15:0]min=0; always @(posedge clk) begin if($signed(din)>max) max=din; else if($signed(din)<min) min=din; end assign dout=max;`endmoduleThe problem in above code is that for example the if condition becomes true for (eg) the 2nd cycle sample value, then max will be assigned the 2nd sample value as max sample value. Now let us consider that input din has max sample value at the 15th cycle of all the 1000 samples. So after the 15th cycle max will contain that max value and the output dout will contain max value after 15th cycle and before 15th cycle it will contain the maximum of the first 14 sample values. I want my output i.e max register to contain only the maximum value i.e the 15th value.       plzz help me to sort out this problem..thanks in advance..  -1down votefavorite (http://stackoverflow.com/questions/37365944/verilog-code-to-find-max-and-min-value-in-an-input?noredirect=1#)   I want to find max and min in input file, read from a memory. This input file containsize 1000 decimal sample values. I have written the following code to find max and min by comparing with a threshold.  module max_min(input clk, input [15:0]din, output [15:0]dout); reg [15:0]max=0; reg [15:0]min=0; always @(posedge clk) begin if($signed(din)>max) max=din; else if($signed(din)<min) min=din; end assign dout=max;`endmoduleThe problem in above code is that for example the if condition becomes true for (eg) the 2nd cycle sample value, then max will be assigned the 2nd sample value as max sample value. Now let us consider that input din has max sample value at the 15th cycle of all the 1000 samples. So after the 15th cycle max will contain that max value and the output dout will contain max value after 15th cycle and before 15th cycle it will contain the maximum of the first 14 sample values. I want my output i.e max register to contain only the maximum value i.e the 15th value.