Hello. I would like to operate time-to-digital converter in FPGA.
My main question is how much time resolution can be taken in a FPGA?
There are two sub-questions.
One is that I see a specification of arria model which can operate at about 1.5GHz.
Then, can I make a fast counter with 667ps(1/1.5GHz) time resolution @1.5GHz from internal PLL?
The other is that can I use sub-phases from internal PLL?
If so, how many?
In my case, I have a MAX10 model (10M50). So I synthesize a 400MHz PLL with 100MHz reference clock.
Then, could I use 4 sub-phases from 400MHz PLL in MAX10?
If so, I guess at least 625ps time resolution can be taken.
Arria 10 I/O PLL can generate a max of 644 MHz for internal clocking (fOUT). I guess you might be mistaking the fVCO number of 1600MHz. Please refer the datasheet.
For the MAX 10 device you can create clocks (5 clocks) with a phase shift of 45 deg. Please refer following link for more information:
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