How to keep logic not being optimized away?

[Altera_Forum]

Hi guys: 

 For some applications, I need insert some logic cells in my design. How to keep these logic?   Another question is anyone know what is the delay range of one logic cell? 4 ns? or other results?!

[Altera_Forum]

Hi Jerry, 

 there are ways to do this but I'd like to recommend that you don't use these. Think again and again if you can avoid combinational delays. The delay depends on the current routing and therefore changes from compilation run to compilation run. Maybe you can describe what you needs to do an the forum users can propose alternate solutions?  Harald

[Altera_Forum]

--- Quote Start ---  Hi guys:   For some applications, I need insert some logic cells in my design. How to keep these logic?   Another question is anyone know what is the delay range of one logic cell? 4 ns? or other results?!  --- Quote End ---    Hi Jerry,  I have a small example attached. Check the settings of:   "Remove redundant logic cells" , must be "off" "Ignore LCELL buffers", must be "off"  You will find the settings : -> more settings  Generally you have to keep in that the resulting delay dependent on a lot of factors:  Device speed, Supply voltage, Temperature, Placement routing .....  Kind regards  GPK

[Altera_Forum]

Harald,Pletz: 

 Thanks for your comments.   I know using combination as delay unit is not a good idea. But our design isn't a sync, in another word, we can't use clock for the delay logic.   And what we want to implement is to delay 32 trigger signals inside CPLD, and each delay time is diffrent. The differ is more than 200 ns.

[Altera_Forum]

Another question is that if i use lcell as the delay chain, i found that the cpld device doesn't have enough resoures ~0~. 

 Just like what Harald said, it seems that we should find other ways to implement it.

[Altera_Forum]

To prevent logic cell optimization precisely for particular nodes, I suggest to use HDL synthesis attributes. 

The below example prevents removal of the signal my_wire. signal my_wire: bit; attribute syn_keep: boolean; attribute syn_keep of my_wire: signal is true; More examples can be found in the Quartus II Software Handbook and in the advanced synthesis cookbook. http://www.altera.com/literature/man...x_cookbook.pdf  P.S.: Because you mentioned CPLDs. Unfortunately, many settings to keep logic cells are ignored by the Quartus CPLD fitter. I'm not sure, if there's a way to achieve it at all. 200 ns would be far above a reasonable logic cell delay anyway.

[Altera_Forum]

Hi FvM: 

 Thanks for ur recommendations.   BTW: The page of the cookbook is not found. pls help to check it.

[Altera_Forum]

I have a issue of how to define the lcell in VHDL?

[Altera_Forum]

I can instantiate the lcell in my vhdl file now. But i can't keep the std_logic type signal such as below: 

signal reg1,reg2,reg3: std_logic; attribute keep : std_logic; attribute keep of reg1 : signal is true; If I do as above the QII will give out below error informations: Error (10476): VHDL error at LcellTest.vhd(32): type of identifier "true" does not agree with its usage as "std_logic" type

[Altera_Forum]

I corrected it.  

The "attribute keep : std_logic;" should be "attribute keep : boolean;"

[Altera_Forum]

--- Quote Start ---  I corrected it.  The "attribute keep : std_logic;" should be "attribute keep : boolean;"  --- Quote End ---     Hi so your design is working? I'd like to make delay chain too. Can you share your design? :)  Thank you, Honza

[Altera_Forum]

--- Quote Start ---  Hi so your design is working? I'd like to make delay chain too. Can you share your design? :)  Thank you, Honza  --- Quote End ---    You can implement delay-chain by using carry chain resource inside of the FPGA.