How to make a custom IP (that integrated with an example design) to create testbench in Arria 10

[Sijith]

Hi,

I have a custom IP of a counter and that connected to the PCIe DMA transfer example design for the  Arria 10 device(I have attached the counter code counter.v with this message). I also added an Avalon FIFO IP that stream data from counter IP to the PCIe DMA transfer example design.

(for the PCIe DMA transfer example design with DDR4, I followed the Chapter-7 section- 7.6 of DE5a_Net_User_Manual.pdf attached)

I have a  Quartus project file  DE5A_NET.qpf and opened it in Quartus Prime Pro.

Then launched Platform Designer System and opened the PCIe DMA transfer example design (ep_g3x8_avmm256_integrated.qsys).

Added Avalon FIFO IP and custom generated IP for  the counter (of which verilog file is attached). Followed steps like System Sync Info, Validate System Integrity and generating HDL.

When I turn on the simulation option in the Generate HDL GUI (turn on means selecting VHDL/Verilog option for simulation. Turned off means selecting none for the simulation option).

I gets some error (attached error_simulation.PNG).

But when just Synthesis option= Verilog and simulation= none, no error. 

I am aware that this is something related to counter code which is synthesis-able only. Also I think it fails in the creating testbench stage. Do you have any suggestion regarding how to make  a custom IP out-of counter.v code (to attach to the example design) that is compatible for both synthesis and simulation? 

 I am working in Arria 10 GX device (10AX115N2F45E1SG) and my host computer is based on windows 10. And I am using Quartus Prime Pro 18.4 version.

[sstrell]

What are your settings in Component Editor?  Perhaps you didn't add simulation files on the Files tab of the Component Editor.

Also helpful to see how your custom component is connected to the rest of the system.

[Sijith]

Thanks for the roping in to help me.  Sorry I missed to add the simulation file while creating custom component. 

Will add and update you the result with adding them. (I am attaching my codes counter and  wrote a simulation file counter_tb (I assume this is what I am suppose to do)). I have attached them as .txt files.

As I am new to Verilog and Quartus Prime, Its highly appreciate any suggestion in the above mentioned codes that is essential for them to be compatible with the remaining part of my design in synthesis and simulation.

As the counter code I have is for converting to custom IP and to integrate to the PCIe DMA transfer example design, do I have to have any special consideration while writing the simulation code?

From "What are your settings in Component Editor?" your question, you meant signal and interface connection? 

Also I am attaching a block symbol of the entire design (avalon_fifo and counter_1 are the extra components I added to the PCIe DMA transfer example design), which have the counter custom IP, Avalon FIFO IP and the PCIe DMA transfer example design.

Please let me know if you need any more information. Thank you.

[RichardTanSY_Intel]

Assuming you created this with the Component Editor, did you specify simulation file(s) on the Files tab? If you did not specify separate simulation files (or chose to use the same files for synthesis and simulation), you would encounter this error.

You can refer to this user guide for more information: 

Please https://www.intel.com/content/www/us/en/docs/programmable/683609/23-1/specify-files-for-simulation-in-the.html

Best Regards,

Richard Tan

p/s: If you find any answers from the community or Intel Support to be helpful, we encourage you to mark them as the best answer or rate them 4/5 in the survey. 

[sstrell · Accepted solution]

No, the file you put in the simulation files section is the design file that should be used when the design is simulated, not a simulation testbench.  This can be the same file as the synthesis file or it could be a different design file optimized for simulation.

[Sijith]

Thank you very much for the info. 

Also I would like to know is there any  Quartus Prime Pro functionality to get a design file optimized for simulation (out of the synthesisable design HDL code) ?

Also you mentioned "different design file optimized for simulation", could you give me an insight of what are those common differences in general cases- Anything coding style or something like that?

I am bit curious that when you asked me about the component editor settings in your first message, is it about the signals and interface settings I used, or the files (synthesis file and simulation file) I used?

Thank you very much

[RichardTanSY_Intel]

I don't think Quartus Prime Pro tool has a function that get a design file optimized for simulation.

You may check this for more information related to Design Optimization.

https://www.intel.com/content/www/us/en/docs/programmable/683641/23-1/faq.html

Best Regards,

Richard Tan

[Sijith]

Thank you very much for helping me to resolve my Issue. As I am comparatively new to Quartus Prime, I would like to know how to simulate my design, once test-bench of a design is created using Platform Designer System.  I would like to elaborate a bit:  my counter.v module is converted to a custom IP and I integrated that with an Avalon FIFO IP in platform designer system. Then synchronized all components and generated HDL and test benches for the design. Also, I compiled the whole design in Quartus Prime Pro. May I know what I have to do to simulate  the whole design? (I have model-sim with my Quartus Prime Pro 18.1.). I have got this doubt since I am using  an off the shelf IP (Avalon FIFO IP) and a custom generated IP in my design.

[sstrell]

I don't know if the design optimization user guide goes into optimizing a design file for simulation.  It probably focuses on optimizing for synthesis.

You'd probably want to check with your simulation tool vendor about optimizing for simulation.  Using an optimized design for simulation can speed up the simulation process.  Obviously, the best would be to use the same design file for both synthesis and simulation.

I was asking about all the component editor settings just to see if there were any other issues.

[Sijith]

Thank you very much for helping me. Now I could get rid of the error by adding the simulation files on the Files tab of the Component Editor (I added as a synthesis file). 

As I am comparatively new to Quartus Prime, I would like to know how to simulate my design, once test-bench of a design is created using Platform Designer System.  I would like to elaborate a bit: My counter.v module is converted to a custom IP and I integrated that with an Avalon FIFO IP in platform designer system. Then synchronized all components and generated HDL and test benches for the design. Also I compiled the whole design in Quartus Prime Pro. May I know how I could get the simulation for the whole design? (I have model-sim with my Quartus Prime Pro 18.1.) . I have got this doubt since I am using  an off the shelf IP (Avalon FIFO IP) and a custom generated IP in my design.

[sstrell]

Check out this training: https://cdrdv2.intel.com/v1/dl/getContent/653122?explicitVersion=true

[RichardTanSY_Intel]

I believe the initial issue has been resolved. Now, I will transition this thread to community support. 

At Intel, we prefer a new case for each unique technical problem, as it aids our case analysis and helps us assess our customer support requirements. 

Could you please raise a separate case for your follow-up technical problem, even though it may or may not be assigned back to me? 

If you have any further questions or concerns, please don't hesitate to reach out. 

Thank you for your understanding and have a great day! 

Best Regards,

Richard Tan