How to simulate the FPGA neural network in Altera

[Altera_Forum]

I want to simulate the some kind of schematics that work by principle of neural networks. I have Altera Quadrus 11. But when trying create some verilog or vhdl code I see that compilation and simulation items of menu is disabled. Should it due to absence of installed device --such warning is appered when creating the project or I do not entered the license properly. If the issue is in not installed device, which one can I use for my student work, how much space it could take. Can I use the web-edition for this purposes, with or without device? 

And the next set of questions relates to the ocding of logical circuit in Altera or Modelsim (which one could I use-- now I have just Model-Sim free edition). The logic circuit should sort analog signals. The other components of circuits is adders with 2 addings and one substraction, and one with adding of all N signals (or non-binary numbers) the N+2 step functions (comparators of amplitude of signals with some x), and one multiplicator and one integrator. So definitive question is the concept and specific of neural networs with back-propagation method in HDL, and other ones is concerning the converting decimal numbers to binary ones (or it could be allowed to be binary from the start), how implement of multiplication for the big coeficent, how the comparator works in Verilog/VHDL, and the most unsure --about integrating the function. I do not exactly even know what is the role of integrator in logic circle (in this case it is connected with the multiplicator and authors even jjust whol ethe whole structure --inverting integrator --*(-Alpha)). Where I could find such examples in VHDL, but it would be better in Verilog, that I studied something. What structure and size of teh whole programming module should be if N (number of sorted items) is 5-6...

[Altera_Forum]

If u are creating a new project,i believe that u already has at least a device family installed in the Quartus because u'll need to choose from the listed part numbers for the design u are creating for. 

If u start from a new file instead of new project, then the uninstalled device warning make more sense to me..in order for u to create a design project,compile it and open it again in future the Quartus needs to be installed with the devices.  Of course the free web edition has limited feature compared to the subsciption edition.u need to check the altera software download webpage to figure out whether web edition really offers what u are trying to do.

[Altera_Forum]

And make sure u open a project NOT a file in the Quartus for u to able to compile the project design.

[Altera_Forum]

Yes I create project not file. But Create not Open. 

And you see this circuit in link. It could be created in Simulink and Micro-cap without any iteration--just integrator should be dependent on time. Can I realize such circuit in altera how structure and complex it could be? What main difficulties should be there?

[Altera_Forum]

http://postimg.org/image/m3qrcpqlj/ -- here is the logic circuit that I need to implement. At least in Micro-cap and simulink it should be done without the iterations and Neural Networks. So Could it be donhe in Altera on Verilog. What is the main difficlulties. S --comparator, there is also inverted integartor on time, that multiplies on coeficient alpha(about 1000)--so I do think it could be easier to do in Verilog then Micro-cap for example as there is no libraries for multiplier, even adder, substractor. The only difficult line is integartor..What would you suggested? Sn+2=x-A; Sn+1=x; depending on the K-Sum of Step functions An-X (intial x should be 0--but it is the main bottleneck as x begin rise on some expotential rule). And I am not aware of the fucntion of analog integrator --al other components should be analog, as the source signals should be constant.

[Altera_Forum]

for Example could I simply use code line "An-Amin+x" in verilog for this adder, and integrator *(-Alpha) for the node around the integartor. The fucntion of integartor is dx=x or x-A; so I do understand that x^2/2=x or x-A; or I am not correct as it is integrating for the time, but internal integral seems to be taking into account as far as I remember since mathematics. Or what such (x)=x should mean? if (x) is the derivative?

[Altera_Forum]

if i were to make a neural network fpga project I would do the following: 

 1) simulate my model in s- domain (continuous time) in Simulink or Matlab 2) convert to z - domain by choosing an appropriate sampling frequency. Convert my continuous functions into discrete functions in z domain. So an integrator is 1/s in s-domain, but in z-domain it is T/(1-z^-1) where T = 1/sampling frequency. That can be modeled as a simple IIR filter. 3) convert my discrete model into a digital model by using the fixed point toolbox  4) once I've verified that my digital simulink model is stable and converges, I would remodel using Altera's advanced DSP blockset. 5) Once confirm it's functionality, I would let Altera's blockset generate VHDL files 6) Import these VHDL files into my Quartus or Qsys project   That maybe a lot more complicated then what you envisioned though...

[Altera_Forum]

I do not know simulink a lot. So I will try to implement it in microcar with the macros of integrator, comparator, adder and so on. But the main issue - shout it be implemented in one cycle or it is needed several iterations. Is it possible to simulate neural network in simulink with the several iterations? As well in altera. As I have just the logic circuit and I need to find the level of shift x that would minimize the function E.

[Altera_Forum]

So what is difference between labview fpga and altera fpga. As I have two task but do not know difference?

[Altera_Forum]

Labview FPGA uses National Instruments (NI) tools and Xilinx FPGAs such as Spartan, Virtex, etc. I've never used Xilinx fpgas before, but I have used Labview as a stand alone solution. Labview is similar to Matlab/ simulink. My guess is that Xilinx provides a tool that can convert Labview designs into synthesizable HDL for their FPGAs. Similarly, Altera provides DSP Builder Blockset that can convert Simulink designs into HDL.

[Altera_Forum]

Thank you for the last cues. But I would also like how to convert labview design to hdl by xilink tools. Can I simply convert by some button or function. Or I should rewrite the whole structure of labview diagrams? And about simulink convertion. Can I convert it also directly. Or I should substitute every block of simulink to dsp blockset? Should I use simulink blocks or matlab code to make file for conversion. As my teacher said that circuit is implemented in simulink code but how? It is easy on his mind.

[Altera_Forum]

The dsp blockset works like any other blockset in Simulink. Place Altera's blocks to create your system. Then simulate your result. You will need a license to generate HDL files from your design. Since you are doing this through the school, you should be able to get a student license or a 60 - day temporary license with the help of your professor. You can place a request with Altera to send you a license for DSP builder. 

 So make your circuit in Simulink using the dsp blockset from Altera. If you've never used simulink before, you should do a quick search, but basically it is a graphical flow program. You place blocks and connect them to indicate data flow/operation.   Not sure how Xilinx and Labview interface, but it is probably the same deal.

[Altera_Forum]

It is easy on his mind-I just overlooked it as I use t9 on my phone so some words are automatic

[Altera_Forum]

Could I convert Simulink blocks (where I composed the workable circuit for signals) to HDL? Where I could download the HDL Converter if I have matlab 6.5, how much size it take? I heard it covert but not all blocks, what are the main issues there—if my scheme has integrator, comparator(> operators), adder, substracter, switch (like selector in Labview), the sources of signals, and its output? Can I do it with the Labview to convert the diagram to HDL. Once more questions relates if it possible to compose analog, not binary, circuit in Altera? For example I heard the Sim2spice for Simuling to change it to FPAA, but I cannot find it anywhere. And I have DSP blockset, but when I launch it I got the error that I cannot find MAtlab—but I have MAtlab 6.5—so what version I should use for Altera 11, and maybe should place the MAtlab in DSP blockset folder? And it is interested what in particular DSP could do with my Simulink Blocks…

[Altera_Forum]

1) Yes there is a tool in Matlab that can convert some Simulink parts to HDL it is called HDL Coder. I've used it, but HDL Coder is not efficient. It generates generic code that is vendor agnostic, meaning you will not be using on board resources efficiently. If you want to target Altera, you are better off using Altera's DSP builder blockset. It will take you the same amount of time make your design using Altera's blocks. Normally, you would need to pay for HDL coder and it is a VERY expensive package - it's not worth the money. 

 2) You should use a recent version of Matlab. So if your Altera version is 13 and you DSP builder version is 13, then use the 2013 version of Matlab. DSP builder can be placed outside of matlab, but you will need to create the right paths. You should do this using the setup_dspba command. You can find the proper commands/files by looking through the DSP builder folders. I'm not sure if DSP builder 11 will work with Matlab 6.5. You should upgrade your Matlab version (one way or another)... Also you need a license to convert files from DSP builder to VHDL. You can get a license from an Altera rep. They can get you a 60 day trial period when you are ready, or you can try to get a student/university license.  3) I have no experience with FPAAs. They are a completely different technology. I don't see why you wouldn't be able to convert your neural net design into a digital circuit and run it on FPGA. Going to FPAA might be a dramatic move.  So in summary, update your Matlab, and set up the right paths for DSP builder. Then you should have no issue working on your design. I know that setting up is frustrating, but you need to make the commitment. You can write a support ticket on Altera's website and ask for specific help on how to set everything up. Also, you can ask if a rep can visit you in person and help you out, especially in a university setting.

[Altera_Forum]

It is provisionally Neural model, it is just the analogous circuit designed in Simulink and maybe could be applied in Micro-Cap. 

Here at Altera forum is the scheme -- so what I would getn if use DSP blockset as the result--hdl code? If use HDL coder --how much code I can get--thousands of line as it is the feature of this prog.language--is it difficult to correct it? So Altera is unable to use analog components as Micro-cap?

[Altera_Forum]

IF you were to simulate your design using DSP builder you will get 1) simulation results, 2) HDL code that can be synthesized for use in a FPGA. 

 You will get the same results with HDL Coder BUT your HDL will be generic and not optimized.  No, you cannot use analog blocks since FPGAs are inherently DIGITAL - time is discrete. Any integration or transfer function that you may use in s-domain (continuous) must be converted to z-domain (discrete). You also have to use the Fixed Point Tool box for both DSP builder and HDL coder since values are not continuous.  You can begin by first building an analog model in Simulink, and then converting to a discrete model using DSP builder.

[Altera_Forum]

The simulation -- what kind of it -- the some graph of digital signals? 

"HDL will be generic and not optimized" -- how to optimize? So could I use matlab 6.5 with dsp builder? So how big work to do I need? But in my Scheme I use S-integrator (continuous) in Simulink should I convert it to Z-integrator? And hwo to do it--I need use some additional clock source? And I have workable block system in Simulink--could you (or somebody else) convert in Dsp if it is not a lot of time to do --that I would see the result? And one more question--I created the same system in Labview --but there is difficulties with arrays despite all should be simple integers--and I would like to create FPGA version of it--but FPGA pallette have no  integrator by time fucntion--so how can I solve this issue? All other operators such as, +,-, *, <, > are present in FPGA palette? And I say about analog system as the subject of my work is about analog paralel system--but it is probably impossible to do it in Labview or Altera --so why I was supposed to do it in LAbview? Despite Simulink has such tool as Sim2Spice --it seems to be for FPAA but I could not find it? And about HDL Coder--from what version of MAtlab(2012a) it is present? And could I just use this version of Simulink and HDL Coder (with or without HDL verifier)? Yet I would be interested in Verilog design but if it not possible it could be possible to use and VHDL? So as I understand to see simulation of HDL conversion of Simulink blocks I need to use or DSp Blockset, Xilix System Generator or HDL coder. What is simpler and better? And what I should do with my continious-time integrator in simulink?

[Altera_Forum]

Lots of questions here. I will try to answer as best I can. 

 HDL coder works with, i think, Matlab 2012a and beyond. I use Matlab 2013b. HDL coder and DSP builder both generate only VHDL code. However, as I've said before, since HDL coder is vendor independent - the code it produces is very generic. It would be very difficult to optimize this code by hand, and will depend on the HDL synthesizer's ability to properly allocated resources. DSP builder is more optimal for Altera devices since it was design by Altera for use with their FPGAs. Therefore, they know the architecture of the chip. Either way you need to upgrade you Matlab to a newer version.  When you build with HDL coder or DSP builder you need to set up a base clock. This is because any discrete system needs a time step. It can be 20ns for example, that would require a 50MHz clock which is not a fast speed for FPGAs. You can use Matlab functions, like c2d( ) and tf2sos ( ) to convert your S - domain transfer functions to Z - domain. The system you create using DSP blockset will look a lot like the Simulink design, but you will be using only the parts provided in the DSP Blockset library.  Once you generate VHDL code from DSP builder, you can mix it with Verilog files if you want. The synthesizer does not care, as long as all modules are properly connected. The easiest approach would be to import your VHDL code to Qsys and integrate it with your other modules.  You cannot use Xilinx system generator with Altera FPGAs, only with Xilinx FPGAs. I assume the tool and the amount of work required is the same. Yes, the process of going from continuous to discrete to HDL is tedious, but it is necessary. IT will depend on the complexity of your design.  I do not know enough about FPAAs to comment on them. But I think your design is feasible in an FPGA. But as I said before, you MUST convert to discrete domain; you will not be able to use continuous time functions.  If you want, you can post your Simulink model (the continuous one) and I can take a look at it.

[Altera_Forum]

To add one thing to krasners post: Mixing VHDL and Verilog cannot be done in the web version of Quartus. So if you use that to actually synthesize the hardware it will not work. 

[edit]This is not true, see next post for explanation[/edit]

[Altera_Forum]

Are you sure about that? I've been doing that on the web version forever. If module A is in verilog and module B is in VHDL and you instantiate both in the Top Module, there is no problem.