How to simulate the FPGA neural network in Altera

[Altera_Forum]

I want to simulate the some kind of schematics that work by principle of neural networks. I have Altera Quadrus 11. But when trying create some verilog or vhdl code I see that compilation and simulation items of menu is disabled. Should it due to absence of installed device --such warning is appered when creating the project or I do not entered the license properly. If the issue is in not installed device, which one can I use for my student work, how much space it could take. Can I use the web-edition for this purposes, with or without device? 

And the next set of questions relates to the ocding of logical circuit in Altera or Modelsim (which one could I use-- now I have just Model-Sim free edition). The logic circuit should sort analog signals. The other components of circuits is adders with 2 addings and one substraction, and one with adding of all N signals (or non-binary numbers) the N+2 step functions (comparators of amplitude of signals with some x), and one multiplicator and one integrator. So definitive question is the concept and specific of neural networs with back-propagation method in HDL, and other ones is concerning the converting decimal numbers to binary ones (or it could be allowed to be binary from the start), how implement of multiplication for the big coeficent, how the comparator works in Verilog/VHDL, and the most unsure --about integrating the function. I do not exactly even know what is the role of integrator in logic circle (in this case it is connected with the multiplicator and authors even jjust whol ethe whole structure --inverting integrator --*(-Alpha)). Where I could find such examples in VHDL, but it would be better in Verilog, that I studied something. What structure and size of teh whole programming module should be if N (number of sorted items) is 5-6...

[Altera_Forum]

I have never tried, but have always read that it is not possible. But if you are able to do so, than I am wrong and you may forget my previous reply.

[Altera_Forum]

So what I should do with my continous time integrator block with simulink? AMybe just to change to Discrete time? Or I need to add some clock to such integrator or just change the block? 

I also found the Filter HDL Coder in Matlab 2009 -- what is the abilities of such programm--can I generate and simulate HDL code, or just generate? I also read about VHDL and VErilog in HDL coder -- why you talk about just of VHDL?

[Altera_Forum]

First express your integrator in discrete domain (z-domain). Yes you have to use discrete time. You need to set up the fixed time step as well. 

 It seems that you really want to use HDL coder. That is fine. In HDL coder you can generate code and simulate your design. However, you will not be able to verify that your model has been accurately converted to HDL. You will need to simulate your HDL in Modelsim or ActiveHDL to validate the conversion. (This is not trivial to do).  I thought HDL coder can only make VHDL code, but if it can make Verilog code then go for it. DSP builder can only make VHDL. Either way, the code will probably be difficult to analyze by hand since the conversion process will generate very non-descriptive register name. It is not easy to read through the generated HDL code.  But to start, first you need to make a continuous simulink model and verify its functionality. Then post it here and I can tell you what to do next.

[Altera_Forum]

So can I generate the HDL just with Filter Design Coder from Matlab2009 -- I have now--it seems generate, and verify on HDL testbench but in Model-Sim. 

Here is my continious time model-- it could be change to discret time--but the results is just simple line and also vertical line so something incorrect, so i left continous time--http://s000.tinyupload.com/?file_id=18188888348335316509

[Altera_Forum]

OK i see what is going on. When you do discrete functions you need to set up the proper fixed time step. If the time step is too large, you will not get the right results. I set the time step to less than 0.001 (i like 0.0001 better, the is 10kHz) and my discrete results match the continuous results. Fixed time step is set in Simulation > Configuration Parameters. 

 I am attaching my discrete model. You are using Matlab 6.5 correct? I am attaching a 2009a version and a 6.5 version. I use 2013b so i have to back convert. Hopefully one of these files works for you.

[Altera_Forum]

My Simulink 5.0 tells me that your MAtlab 6.5 version is newer then mine -- 6.5.0.18091 (R13). Where I should note 0.001 -- in Max, Min, Initial Step in Simulation Parameters? I thought early iy should be in Sample Time as by default it seems to be 1 (inherited --> -1). But it doesnot work now. 

But I located my Mdl file to convert it to VHDL and test it .. in DSP, ModelSim, SystemGenerator

[Altera_Forum]

Ok you definitely need to upgrade matlab. Also in the simulation configuration panel, you are probably still using "Variable Step". You can change that to "Fixed Step" then use 0.001. 

 Sample Time is in "seconds". So Sample time of 1 = 1 second per step. Sample Time of 0.001 is 1/1000 of second per step. Sample Time of -1 mean use the same sample time as the block before or as set in the configurations.  Yeah your simulimk/matlab is so old that I can't even back convert it that far.

[Altera_Forum]

Yes I applied fixed-time step yet to Discrete time integrator and nothing changes . I see 3 lines horizontally, and several blue lines vertically. 

Anyway you can simulate HDL with my example and show me the results? And I have not installed MAtlab2009 with Filter design HDL coder -- could I use this for generation HDL and then to simulate on Model Sim?

[Altera_Forum]

Yes I opened you discrete integrator that works fine but in Matlab2009.  

I do not know why it is not works with Matlab 6.5 So How can I wright the path to MAtlab 6.5 or 7.8 portable in DSP Blockset. Except the discrete time parameters it needs also additional parameters in Simulation settings for farther HDL generation in DSP. Anyway --why you could not launch the blocksystem with generated HDL code in MODel iM to allow me to view the results in Altera. As I have generated Verilog code in Fileter Design Coder but after automatic launch of this file in ModelSim the app hanged up. And you said the code is to generic or so. Anyway what I could get when see the HDL simulation-- what is rationale of this rectangle signals -- should they resemble my display of signals like in Scope block in Simulink?

[Altera_Forum]

I don't fully understand what you are saying here. 

 But here is what I gather:  1) The discrete sinmulink44_d2009a.mdl file working in Matlab 2009. This is good.  2) You some how generated HDL from this design? Not sure if this is what you are saying. But in my opinion you should NOT have been able to do this. This is because although the design is discrete (set sample time), it is NOT DIGITAL (values/amplitudes being fixed point). Think for an ADC (analog to digital converter). It's job is to convert continuous real world values in to digital signals. So if you have an 8 bit ADC, it can only create 256 values (2^8), so your real world signal will be binned into one of the 256 possible outcomes.  The fixed point toolbox in matlab can help you with that. In the simulink design you have to specify your "output data type". You can do this individually for all constants and arithmetic blocks by double - clicking them, then going to "signal attributes" tabs and then under "output data type" selecting fixdt(a,b,c). a is signed (1) or unsigned (0). b is total bit length, c is fractional length. So if you use fixdt (1, 4, 2) this means you will have 4 bits - 1 is for the sign, 2 are for the fraction. If you click the ">>" box you can get details about your allowable range using these parameters. So fixdt(1,4,2) will allow to have ranges from -2 to 1.75 with a digital step of 0.25 (1/2 ^ 2). Think of it as 4 spaces where the first one is the sign, second one is the integer and the last two are you decimal place in the power of 2: (sign) _ . _ _   What is important to note is what values you can be getting especially when you multiply. For example if you were to multiply two fixdt(1,4,2) numbers together, your output will no longer be in the -2 to 1.75 range. It will be in the -3.5 to 4 range. There for you will need to adjust your output data type. Normally you can just add the number data types together: so you will get fixdt(1, 4+4, 2+2) = fixdt(1,8,4). In DSP builder can take care of that better and simulink on its own does.  Once you do that and verify that that works, then you can proceed with generating HDL. Not trivial, right? It is not easy going from continuous to digital domain (time and values are discrete), but it is possible.  So i am attaching the digital version of your design (discrete in time and in values). For constants I used fixdt(1,12,6) and for multiplication i used fixdt(1,24,12). This is probably too much range, but you can adjust as you like. Let me know if it works for you. Remember you MUST have the Fixed Point Toolbox!

[Altera_Forum]

I have converted yesterday my Simulink design to Verilog file foe about 8000 lines. Is it incorrect? It even automatically launched in Model sim but it said there is no design files. And to add wave window I do not know through menu. Anyway what such quadratic shaped signals could show in HDL simulation--could it show the decreasing of signal as it is in Simulink? 

I appeciate your fixdt conversion but I do not understand how do you do it. You apply it to adders, integartor, constants, gain. But why some is 1,12,24 but other 1,6,12--what it means? If so could I now correctly convert it to HDL. And one more note--the if-else blcok should be replaced by two switch blocks--1-3 input like. And what about DSP--should I also convert to fixdt for it? Where I could find fine tutorial for it? And yet the question again--how can I note the Matlab path for Dsp Blockset? Now I have Matlab2009a and it has more opportunities, such as fixdt, Simulink Fixed Point (with reference to Block Libarry), Matlab fixed-point but just help

[Altera_Forum]

Here is the Simulink design without if-else but with 2 switchs--but works the same -- 

and is simplified. http://s000.tinyupload.com/?file_id=18120771512038272863 And what about dsp blockset--it doesnt see as I have portab version of Matlab. Probably it is impossible to correct it.

[Altera_Forum]

OK you seem to not understand the fundamentals of FPGAs. 

 HDL is a hardware - description language. It isn't software. Hardware needs a defined input and an output. Right now it simulink your "inputs" are some constants, but when you convert to HDL using HDLCoder you basically have a system without any "input ports" and "output ports". This means that when the synthesizer looks at your design it sees it doing nothing.  Since the digital design works (sinmulink44_dig2009a.mdl) you need to replace your constant inputs with input ports (look in the simulink library) and replace the output scope you have with an output port. Set their data types to fixdt(1,12,6). Then regenerate the HDL. It should recognize several 12 - bit inputs (input1, input2, input3....) and one 12 - bit output. Then you can send this to Modelsim and look at each 12 -bit bus.  If you need more explanation about fixed point representation just search "matlab fixed point toolbox" on google. There are plenty examples and explanations. Altera's DSP blockset also needs fixed point toolbox.

[Altera_Forum]

Should fixed point toolbox convert my simulink design automatically? It should probably present on my Matlab 2009a? How launch it? 

On FPGA--yes I just read about it and I do not know how many inputs and outputs it has? But as far as I inderstand it is consisted with some blocks that could do logical functions (<,+,*). But why it should has several input (I need 6 ones as well as such number of output), and just 1 output? Why iy should be 12-bit? And retuening to my circuit in Simulink how integrator by time could be realized there on FPGA, so with the help of HDL.  Yes maybe I can use input ports instead the inputs in Simulink (MAtlab 2009a), as previous one do not have even fixdt. But what can I get in Model SIm --waht this wave could show. How my wave (graph) in Simulink could be different with ModelSim after HDL conversion as I see the quadratic waves but the same level. And yet another question: Can I launch DSP Blockset and just only then connect to MAtlab?

[Altera_Forum]

No. You still need to convert manually to fixed point. It is a toolbox in Matlab. Type "ver" in the command window to see what toolboxes you have. It should include Fixed-Point Designer. 

 For the inputs and outputs I was talking about YOUR design. It have several inputs (which you currently set to constants) and 1 output (which u connect to a scope). I used 12 bits because I didn't want to spend a lot of time picking the proper bit widths. With fixdt(1,12,6) i can cover -32 to 32 - (1/2)^6 with the resolution of (1/2)^6  In HDL one of your basic inputs is a CLOCK, you would externally drive this with some clock. It may will be w/e you want it to be. However, the z -domain representation of the integrator will change with the clock frequency you choose b/c an integrator is T/(1-z^-1) where T is 1/clock frequency. Right now the simulink is for a clock frequency of 10kHz, which is much slower than the max clock frequency that an FPGA can use.  Modelsim shows you individual bits ( 0's and 1's ). To actually see meaningful information you need to group the bits. So if your output is 12 bits you will need to group output[11] thru output[0] into a single bus.  DSP builder acts like a library in Matlab. You need to tell matlab which folder it is located in.

[Altera_Forum]

How to tell Matlab where my DSP blockset is located? If I should do it manually what is the sense of Fixed-Point toolbox? 

The objective of this KWTA circuit is to show K biggest signals (numbers) among N. So if K=4, and N=7, just 4 signals should be above the 0 level, so what is the sense to transform to logic signals as the analog show the real decrease of signal. If so -- how to group them? And I could dsiplay not in one Scope but I should identify this signals-- maybe I could do it by some marker -- 3-bit number (8 signals) -- and then show they are above the 0 level. Anyway the final task is to sort this signal in decresing order, so at first palce will be biggset signal, then 2nd biggest and so on.. But in theory I should do it converting the K biggest signals to 1, and other to 0, then by substracting the K from K+1 and I will be get this K+1 sorted number. Even in Simulink this comparator should compare with 0, so it turns the logical function. So how then to group it?

[Altera_Forum]

Fixed point toolbox is the solver engine. If you don't have it, the simulation won't run. To add DSP builder use "Set Paths" >> All folders with subfolders >> Find your DSP builder folder >> OK 

 So based on what you said, you are trying to replicate the algorithm in the following paper: "A discrete-time dynamic K-winners-take-all neural circuit" Pavlo V. Tymoshchuk 2009. Correct? If so, Figure 2 from this paper shows you the digital implementation of this neural network... Here a1, a2,....aN are your input ports (N inputs). and b1,b2,....bN are your output ports (MY BAD, i said 1 output last time).... Out of these N outputs you will select the K largest b values.  Actually the sorting algorithm might be a little more difficult than your neural network, b/c you have to sort the b outputs and record their initial positions to finally sort the a inputs.

[Altera_Forum]

Despite I added path it doesnot work with Matlab 6.5.  

I do not undestand why do we need this fixed point toolbox when we ned do it manually, but probably in 2009a it should to be. If you transferred to discrete time could you generate and simulate this HDL in ModelSim or DSP Blockset to help me to see the results in binary realization?

[Altera_Forum]

DSP builder won't work with Matlab 6.5... It needs something recent. I used Matlab 2013b. 

 The reason you still need fixed point toolbox because matlab can't interpret fixed point math without it. On its own Matlab can only do floating point math. These operations may look the same, but they work very differently. Fixed point toolbox is an addition to matlab to expand its abilities.  I can try to generate a dsp blockset model. It will take me some time, i'm pretty busy. Meanwhile you need to specify the# of input you need (parameter N in the model description above). That will be fixed. I think currently you have 6 inputs, correct?

[Altera_Forum]

Also I think you need to revise your model. Based on Figure 2 of the paper I attached, the large accumulator is the summation of b1 through bN, AND 2K - N... 

 R = 2K - N - sum (sgn(b1)+sgn(b2)+sgn(b3)+....sgn(bN)); where sgn is the sign of the number (1 if >0, 0 if = 0, -1 if < 0)  You neglected the -N term.......

[Altera_Forum]

No it is something another algorithm, probably revised. 

The sorting of the inputs is the second task. Despite the first task is to show K (if 2), then 2 biggest inputs, that should be 2 outputs that is bigger than 0. So I should have N such circuits. After it I shoudl do sorting. But now I should have at least one such scheme. So it should have K outputs higher han o, and N-K outpts lower than 0 or just 0. I hoped that Fixed Point toolbox should have some automatic function to convert to fixed point, or I should do it by right click of every block and even add some additional blocks as Convert etc.