How to use anything other than the dedicated refclk with Stratic GX Transceiver

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CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

How to use anything other than the dedicated refclk with Stratic GX Transceiver

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Hello,

I've been working on a design on the Stratix V GX SI Development Board. On this board, there exists a 644MHz refclock on the refclock input for the bank that I wish to use. I need to feed a different refclock to it, but have been utterly unable to get any alternate design to pass the Quartus fitter, even though according to documentation it should be possible to do so. I can't find any design examples on how to get this to work.

I've tried using a fractional PLL output, and I've tried using the ALTCLKCTRL component.

What am I missing?

Thanks in advance,

Ray

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