Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
21602 讨论

I/O PIN data output delay is so large (cyclone IV)

JJin01
初学者
1,152 次查看
 
0 项奖励
1 回复
YuanLi_S_Intel
768 次查看
Hi Jongwoo Jin, Apologize that i do not understand the inquiry. The output delay is affected by several factor such as the load Capacitance, trace length and etc. Regards, YL
0 项奖励
回复